CY7C1012AV33
512K x 24 Static RAM
power-down feature that significantly reduces power
consumption when deselected.
Features
• High speed
Writing the data bytes into the SRAM is accomplished when
the chip select controlling that byte is LOW and the write
enable input (WE) input is LOW. Data on the respective
input/output (I/O) pins is then written into the location specified
on the address pins (A0–A18). Asserting all of the chip selects
LOW and write enable LOW will write all 24 bits of data into
the SRAM. Output enable (OE) is ignored while in WRITE
mode.
— tAA = 8 ns
• Low active power
— 1080 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Data bytes can also be individually read from the device.
Reading a byte is accomplished when the chip select
controlling that byte is LOW and write enable (WE) HIGH while
output enable (OE) remains LOW. Under these conditions, the
contents of the memory location specified on the address pins
will appear on the specified data input/output (I/O) pins.
Asserting all the chip selects LOW will read all 24 bits of data
from the SRAM.
• Easy memory expansion with CE0, CE1 and CE2
features
• Available in non Pb-free 119 ball PBGA.
Functional Description
The 24 I/O pins (I/O0–I/O23) are placed in a high-impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For further details,
refer to the truth table of this data sheet.
The CY7C1012AV33 is a high-performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is
separately controlled by the individual chip selects (CE0, CE1,
CE2). CE0 controls the data on the I/O0–I/O7, while CE1
controls the data on I/O8–I/O15, and CE2 controls the data on
the data pins I/O16–I/O23. This device has an automatic
TheCY7C1012AV33isavailableinastandard119-ballPBGA.
Functional Block Diagram
INPUT BUFFER
A
0
A
1
A
2
I/O –I/O
0
7
A
3
512K x 24
ARRAY
A
4
I/O –I/O
8
15
A
5
A
6
I/O –I/O
16
23
A
7
A
8
A
9
CE , CE , CE
2
0
1
COLUMN
DECODER
WE
OE
CONTROL LOGIC
Selection Guide
–8
8
–10
10
Unit
ns
Maximum Access Time
Maximum Operating Current
Commercial
300
300
50
275
275
50
mA
Industrial
Maximum CMOS Standby Current
Commercial/Industrial
mA
Cypress Semiconductor Corporation
Document #: 38-05254 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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