Datasheet > CY7C1012AV33-15BGI

CY7C1012AV33-15BGI

更新时间： 2024-11-28 10:19:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
9页	434K
描述
Standard SRAM, 512KX24, 15ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

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PRELIMINARY

CY7C1012AV33

512K x 24 Static RAM

power-down feature that significantly reduces power

consumption when deselected.

Features

• High speed

Writing the data bytes into the SRAM is accomplished when

the chip select controlling that byte is LOW and the write

enable input (WE) input is LOW. Data on the respective

input/output (I/O) pins is then written into the location specified

on the address pins (A₀–A₁₆). Asserting all of the chip selects

LOW and write enable LOW will write all 24 bits of data into the

SRAM. Output enable (OE) is ignored while in WRITE mode.

— t_AA= 10 ns

• Low active power

— 180 mW (max.)

• Operating voltages of 3.3 +/- 0.3V

• 2.0V data retention

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE₁, CE₂and CE₃

features

Data bytes can also be individually read from the device.

Reading a byte is accomplished when the chip select

controlling that byte is LOW and write enable (WE) HIGH while

output enable (OE) remains LOW. Under these conditions, the

contents of the memory location specified on the address pins

will appear on the specified data input/output (I/O) pins.

Asserting all the chip selects LOW will read all 24 bits of data

from the SRAM.

Functional Description

The CY7C1012AV33 is a high-performance CMOS static RAM

organized as 512K words by 24 bits. Each data byte is

separately controlled by the individual chip selects (CE₀, CE₁,

CE₂). CE₀controls the data on the I/O₀–I/O₇, while CE₁

controls the data on I/O₈–I/O₁₅, and CE₂controls the data on

the data pins I/O₁₆–I/O₂₃. This device has an automatic

The 24 I/O pins (I/O₀–I/O₂₃) are placed in a high-impedance

state when all the chip selects are HIGH or when the output

enable (OE) is HIGH during a READ mode. For further details,

refer to the truth table of this datasheet.

The CY7C1012AV33 is available in a standard 119-ball BGA.

Functional Block Diagram

INPUT BUFFER

I/O –I/O

512K x 24

ARRAY

I/O –I/O

4096 x 4096

I/O –I/O

CE , CE , CE

COLUMN

DECODER

CONTROL LOGIC

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05254 Rev. **

Revised March 6, 2002

12 3 4 5 6 7...9

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与CY7C1012AV33-15BGI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1012AV33-8BGC	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV33-8BGCT	CYPRESS	获取价格	Standard SRAM, 512KX24, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1012AV33-8BGI	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV33-8BGIT	CYPRESS	获取价格	Standard SRAM, 512KX24, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1012DV33	CYPRESS	获取价格	12-Mbit (512K X 24) Static RAM
CY7C1012DV33_07	CYPRESS	获取价格	12-Mbit (512K X 24) Static RAM
CY7C1012DV33_09	CYPRESS	获取价格	12-Mbit (512K X 24) Static RAM
CY7C1012DV33-10BGXI	CYPRESS	获取价格	12-Mbit (512K X 24) Static RAM
CY7C1012DV33-10BGXIT	CYPRESS	获取价格	暂无描述
CY7C1012DV33-8BGXC	CYPRESS	获取价格	12-Mbit (512K X 24) Static RAM

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