Datasheet > CY7C1012DV33

CY7C1012DV33

更新时间： 2024-11-24 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	304K
描述
12-Mbit (512K X 24) Static RAM

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CY7C1012DV33 数据手册

CY7C1012DV33

PRELIMINARY

12-Mbit (512K X 24) Static RAM

power-down feature that significantly reduces power

consumption when deselected.

Features

• High speed

Writing the data bytes into the SRAM is accomplished when

the chip select controlling that byte is LOW and the write

enable input (WE) input is LOW. Data on the respective

input/output (I/O) pins is then written into the location specified

on the address pins (A₀–A₁₈). Asserting all of the chip selects

LOW and write enable LOW will write all 24 bits of data into

the SRAM. Output enable (OE) is ignored while in WRITE

mode.

— t_AA= 8 ns

• Low active power

— I_CC= 185 mA @ 8 ns

• Low CMOS standby power

— I_SB2= 25 mA

• Operating voltages of 3.3 ± 0.3V

• 2.0V data retention

Data bytes can also be individually read from the device.

Reading a byte is accomplished when the chip select

controlling that byte is LOW and write enable (WE) HIGH while

output enable (OE) remains LOW. Under these conditions, the

contents of the memory location specified on the address pins

will appear on the specified data input/output (I/O) pins.

Asserting all the chip selects LOW will read all 24 bits of data

from the SRAM.

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Available in Lead Pb-Free Standard 119-ball PBGA

Functional Description

The 24 I/O pins (I/O₀–I/O₂₃) are placed in a high-impedance

state when all the chip selects are HIGH or when the output

enable (OE) is HIGH during a READ mode. For further details,

refer to the truth table of this data sheet.

The CY7C1012DV33 is a high-performance CMOS static

RAM organized as 512K words by 24 bits. Each data byte is

separately controlled by the individual chip selects (CE₁, CE₂,

CE₃). CE₁controls the data on the I/O₀–I/O₇, while CE₂

controls the data on I/O₈–I/O₁₅, and CE₃controls the data on

the data pins I/O₁₆–I/O₂₃. This device has an automatic

Functional Block Diagram

INPUT BUFFER

I/O₀–I/O₇

512K x 24

ARRAY

I/O₈–I/O₁₅

I/O₁₆–I/O₂₃

CE₁, CE₂, CE₃

COLUMN

DECODER

CONTROL LOGIC

Selection Guide

–8

Unit

Maximum Access Time

Maximum Operating Current

185

Maximum CMOS Standby Current

Cypress Semiconductor Corporation

Document #: 38-05610 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 4, 2006

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与CY7C1012DV33相关器件

型号	品牌	获取价格	描述	数据表
CY7C1012DV33_07	CYPRESS	获取价格	12-Mbit (512K X 24) Static RAM
CY7C1012DV33_09	CYPRESS	获取价格	12-Mbit (512K X 24) Static RAM
CY7C1012DV33-10BGXI	CYPRESS	获取价格	12-Mbit (512K X 24) Static RAM
CY7C1012DV33-10BGXIT	CYPRESS	获取价格	暂无描述
CY7C1012DV33-8BGXC	CYPRESS	获取价格	12-Mbit (512K X 24) Static RAM
CY7C101-35DC	ETC	获取价格	x4 SRAM
CY7C101-35DMB	ETC	获取价格	x4 SRAM
CY7C101-35LC	ETC	获取价格	x4 SRAM
CY7C101-35LMB	ETC	获取价格	x4 SRAM
CY7C101-35PC	ETC	获取价格	x4 SRAM

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