Datasheet > 暂无类别数据> CY7C1012DV33-10BGXIT

CY7C1012DV33-10BGXIT

更新时间： 2024-09-18 13:07:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	306K
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CY7C1012DV33

12-Mbit (512K X 24) Static RAM

Features

Functional Description

■

High speed

t_AA= 10 ns

Low active power

I_CC= 175 mA at 10 ns

Low CMOS standby power

I_SB2= 25 mA

The CY7C1012DV33 is a high performance CMOS static RAM

organized as 512K words by 24 bits. Each data byte is separately

controlled by the individual chip selects (CE₁, CE₂, and CE₃).

CE₁controls the data on the I/O₀– I/O₇, while CE₂controls the

data on I/O₈– I/O₁₅, and CE₃controls the data on the data pins

I/O₁₆– I/O₂₃. This device has an automatic power down feature

that significantly reduces power consumption when deselected.

❐

Writing the data bytes into the SRAM is accomplished when the

chip select controlling that byte is LOW and the write enable input

(WE) input is LOW. Data on the respective input and output (I/O)

pins is then written into the location specified on the address pins

(A₀– A₁₈). Asserting all of the chip selects LOW and write enable

LOW writes all 24 bits of data into the SRAM. Output enable (OE)

is ignored while in WRITE mode.

■

Operating voltages of 3.3 ± 0.3V

2.0V data retention

Automatic power down when deselected

TTL compatible inputs and outputs

Available in Pb-free standard 119-ball PBGA

Data bytes are also individually read from the device. Reading a

byte is accomplished when the chip select controlling that byte

is LOW and write enable (WE) HIGH, while output enable (OE)

remains LOW. Under these conditions, the contents of the

memory location specified on the address pins appear on the

specified data input and output (I/O) pins. Asserting all the chip

selects LOW reads all 24 bits of data from the SRAM.

The 24 I/O pins (I/O₀– I/O₂₃) are placed in a high impedance

state when all the chip selects are HIGH or when the output

enable (OE) is HIGH during a READ mode. For more infor-

mation, see the Truth Table on page 8.

Logic Block Diagram

INPUT BUFFER

I/O₀– I/O₇

I/O₈– I/O₁₅

I/O₁₆– I/O₂₃

512K x 24

ARRAY

A_(9:0)

CE₁, CE₂, CE₃

COLUMN

DECODER

CONTROL LOGIC

A_(18:10)

Cypress Semiconductor Corporation

Document Number: 38-05610 Rev. *D

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised November 6, 2008

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