Datasheet > CY7C1012AV33_11

CY7C1012AV33_11

更新时间： 2024-11-27 09:43:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	467K
描述
512 K × 24 Static RAM TTL-compatible inputs and outputs

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CY7C1012AV33_11 数据手册

CY7C1012AV33

512 K × 24 Static RAM

512

K × 24 Static RAM

Features

Functional Description

■ High speed

❐ t_AA= 8 ns

The CY7C1012AV33 is a high-performance CMOS static RAM

organized as 512 K words by 24 bits. Each data byte is

separately controlled by the individual chip selects (CE₀, CE₁,

CE₂). CE₀controls the data on the I/O₀–I/O₇, while CE₁controls

the data on I/O₈–I/O₁₅, and CE₂controls the data on the data

pins I/O₁₆–I/O₂₃. This device has an automatic power-down

feature that significantly reduces power consumption when

deselected.

■ Low active power

❐ 1080 mW (max)

■ Operating voltages of 3.3 ± 0.3 V

■ 2.0 V data retention

Writing the data bytes into the SRAM is accomplished when the

chip select controlling that byte is LOW and the write enable input

(WE) input is LOW. Data on the respective input/output (I/O) pins

is then written into the location specified on the address pins

(A₀–A₁₈). Asserting all of the chip selects LOW and write enable

LOW will write all 24 bits of data into the SRAM. Output enable

(OE) is ignored while in WRITE mode.

■ Automatic power-down when deselected

■ TTL-compatible inputs and outputs

■ Easy memory expansion with CE₀, CE₁and CE₂features

■ Available in non Pb-free 119 ball PBGA.

Data bytes can also be individually read from the device.

Reading a byte is accomplished when the chip select controlling

that byte is LOW and write enable (WE) HIGH while output

enable (OE) remains LOW. Under these conditions, the contents

of the memory location specified on the address pins will appear

on the specified data input/output (I/O) pins. Asserting all the chip

selects LOW will read all 24 bits of data from the SRAM.

The 24 I/O pins (I/O₀–I/O₂₃) are placed in a high-impedance

state when all the chip selects are HIGH or when the output

enable (OE) is HIGH during a READ mode. For further details,

refer to the truth table of this data sheet.

The CY7C1012AV33 is available in a standard 119-ball PBGA.

Functional Block Diagram

INPUT BUFFER

I/O –I/O

512K x 24

ARRAY

I/O –I/O

CE , CE , CE

COLUMN

DECODER

CONTROL LOGIC

Cypress Semiconductor Corporation

Document Number: 38-05254 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 7, 2011

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与CY7C1012AV33_11相关器件

型号	品牌	获取价格	描述	数据表
CY7C1012AV33-10BGC	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV33-10BGCT	CYPRESS	获取价格	Standard SRAM, 512KX24, 10ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1012AV33-10BGI	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV33-12BGC	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV33-12BGI	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV33-15BGC	CYPRESS	获取价格	Standard SRAM, 512KX24, 15ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1012AV33-15BGI	CYPRESS	获取价格	Standard SRAM, 512KX24, 15ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1012AV33-8BGC	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV33-8BGCT	CYPRESS	获取价格	Standard SRAM, 512KX24, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1012AV33-8BGI	CYPRESS	获取价格	512K x 24 Static RAM

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