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CY62256VN

更新时间: 2024-09-14 04:38:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 645K
描述
256K (32K x 8) Static RAM

CY62256VN 数据手册

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CY62256VN  
256K (32K x 8) Static RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
The CY62256VN family is composed of two high-performance  
CMOS static RAM’s organized as 32K words by 8 bits. Easy  
memory expansion is provided by an active LOW chip enable  
(CE) and active LOW output enable (OE) and tri-state drivers.  
These devices have an automatic power-down feature,  
reducing the power consumption by over 99% when  
deselected.  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
— Automotive-E: –40°C to 125°C  
• Speed: 70 ns  
An active LOW write enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins are present on the eight data input/output pins.  
• Low voltage range: 2.7V–3.6V  
• Low active power and standby power  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Available in standard Pb-free and non Pb-free 28-lead  
(300-mil) narrow SOIC, 28-lead TSOP-I and 28-lead  
Reverse TSOP-I packages  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH.  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
INPUTBUFFER  
A
A
A
10  
9
8
A
7
6
5
A
32K x 8  
ARRAY  
A
A
A
A
4
3
2
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-06512 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 3, 2006  
[+] Feedback  

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