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CY62256VNLL-70SNXCT PDF预览

CY62256VNLL-70SNXCT

更新时间: 2024-09-14 20:11:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
13页 351K
描述
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28

CY62256VNLL-70SNXCT 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.62
最长访问时间:70 nsJESD-30 代码:R-PDSO-G28
JESD-609代码:e3/e4长度:17.9324 mm
内存密度:262144 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:28字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:2.794 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN/NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:7.5057 mmBase Number Matches:1

CY62256VNLL-70SNXCT 数据手册

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CY62256VN  
256K (32K x 8) Static RAM  
Features  
Functional Description  
Temperature Ranges  
The CY62256VN[1] family is composed of two high performance  
CMOS static RAM’s organized as 32K words by 8 bits. Easy  
memory expansion is provided by an active LOW chip enable  
(CE) and active LOW output enable (OE) and tristate drivers.  
These devices have an automatic power down feature, reducing  
the power consumption by over 99% when deselected.  
Commercial: 0°C to 70°C  
Industrial: –40°C to 85°C  
Automotive-A: –40°C to 85°C  
Automotive-E: –40°C to 125°C  
Speed: 70 ns  
An active LOW write enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location addressed  
by the address present on the address pins (A0 through A14).  
Reading the device is accomplished by selecting the device and  
enabling the outputs, CE and OE active LOW, while WE remains  
inactive or HIGH. Under these conditions, the contents of the  
location addressed by the information on address pins are  
present on the eight data input/output pins.  
Low Voltage Range: 2.7V to 3.6V  
Low Active Power and Standby Power  
Easy Memory Expansion with CE and OE Features  
TTL Compatible Inputs and Outputs  
Automatic Power Down when Deselected  
CMOS for Optimum Speed and Power  
The input/output pins remain in a high impedance state unless  
the chip is selected, outputs are enabled, and write enable (WE)  
is HIGH.  
Available in Standard Pb-free and non Pb-free 28-Pin (300-mil)  
Narrow SOIC, 28-Pin TSOP-I, and 28-Pin Reverse TSOP-I  
Packages  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
INPUTBUFFER  
A
A
A
10  
9
8
A
7
6
5
A
32K x 8  
ARRAY  
A
A
A
A
4
3
2
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
.
Note  
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-06512 Rev. *B  
198 Champion Court  
San Jose  
,
CA 95134-1709  
408-943-2600  
Revised September 25, 2009  
[+] Feedback  
 

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