5秒后页面跳转
捷配首页

Datasheet > CY62138F
CY62138F PDF预览

CY62138F

更新时间： 2024-11-05 04:53:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 841K
描述
2-Mbit (256K x 8) Static RAM

阅读下载

中文翻译

获取价格

CY62138F 数据手册

 浏览型号CY62138F的Datasheet PDF文件第2页浏览型号CY62138F的Datasheet PDF文件第3页浏览型号CY62138F的Datasheet PDF文件第4页浏览型号CY62138F的Datasheet PDF文件第5页浏览型号CY62138F的Datasheet PDF文件第6页浏览型号CY62138F的Datasheet PDF文件第7页 
CY62138F MoBL®  
2-Mbit (256K x 8) Static RAM  
Features  
Functional Description [1]  
• High speed: 45 ns  
The CY62138F is a high performance CMOS static RAM  
organized as 256K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power down feature that significantly  
reduces power consumption when addresses are not toggling.  
Placing the device into standby mode reduces power  
consumption by more than 99% when deselected (CE1 HIGH  
or CE2 LOW).  
• Wide voltage range: 4.5 V – 5.5 V  
• Pin compatible with CY62138V  
• Ultra low standby power  
— Typical standby current: 1 µA  
— Maximum standby current: 5 µA  
• Ultra low active power  
— Typical active current: 1.6 mA @ f = 1 MHz  
• Easy memory expansion with CE1, CE2, and OE features  
• Automatic power down when deselected  
• CMOS for optimum speed and power  
To write to the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Write Enable (WE) inputs LOW. Data on the eight  
IO pins (IO0 through IO7) is then written into the location  
specified on the address pins (A0 through A17).  
• Available in Pb-free 32-pin SOIC and 32-pin TSOP II  
packages  
To read from the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and output enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins appear on  
the IO pins.  
The eight input and output pins (IO0 through IO7) are placed  
in a high impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW and CE2 HIGH and WE  
LOW).  
Logic Block Diagram  
IO  
0
DATA IN DRIVERS  
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO  
1
IO  
2
256K x 8  
ARRAY  
IO  
3
IO  
IO  
IO  
IO  
4
5
6
7
A
A
A
9
10  
11  
CE  
CE  
1
2
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Note  
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-13194 Rev. *A  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised March 26, 2007  
[+] Feedback  
1234567...10

中文翻译

下载PDF

与CY62138F相关器件

型号 品牌 获取价格 描述 数据表
CY62138F_09 CYPRESS

获取价格

 		2-Mbit (256K x 8) Static RAM
CY62138F_10 CYPRESS

获取价格

 		2-Mbit (256K x 8) Static RAM
CY62138F_11 CYPRESS

获取价格

 		2-Mbit (256 K x 8) Static RAM Automatic power down when deselected
CY62138F_13 CYPRESS

获取价格

 		2-Mbit (256 K x 8) Static RAM
CY62138FLL CYPRESS

获取价格

 		2-Mbit (256K x 8) Static RAM
CY62138FLL-45SXI CYPRESS

获取价格

 		2-Mbit (256K x 8) Static RAM
CY62138FLL-45SXI INFINEON

获取价格

 		Asynchronous SRAM
CY62138FLL-45SXIT INFINEON

获取价格

 		Asynchronous SRAM
CY62138FLL-45ZSXI CYPRESS

获取价格

 		2-Mbit (256K x 8) Static RAM
CY62138FLL-45ZSXIT CYPRESS

获取价格

 		Standard SRAM, 256KX8, 45ns, CMOS, PDSO32

与CY62138F相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证