Datasheet > CY62138F_13

CY62138F_13

更新时间： 2024-11-05 12:52:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
16页	628K
描述
2-Mbit (256 K x 8) Static RAM

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CY62138F_13 数据手册

CY62138F MoBL^®

2-Mbit (256 K × 8) Static RAM

2-Mbit (256

K × 8) Static RAM

Features

Functional Description

■ High speed: 45 ns

The CY62138F is a high performance CMOS static RAM

organized as 256K words by 8 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^®) in portable

applications. The device also has an automatic power down

feature that significantly reduces power consumption when

addresses are not toggling. Placing the device into standby

mode reduces power consumption by more than 99% when

deselected (CE₁HIGH or CE₂LOW).

■ Wide voltage range: 4.5 V to 5.5 V

■ Pin compatible with CY62138V

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 5 A

■ Ultra low active power

❐ Typical active current: 1.6 mA @ f = 1 MHz

To write to the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location specified

on the address pins (A₀through A₁₇).

■ Easy memory expansion with CE₁, CE_2,and OE features

■ Automatic power down when deselected

To read from the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and output enable (OE) LOW while forcing Write Enable

(WE) HIGH. Under these conditions, the contents of the memory

location specified by the address pins appear on the I/O pins.

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

■ Available in Pb-free 32-pin SOIC and 32-pin thin small outline

package (TSOP) II packages

The eight input and output pins (I/O₀through I/O₇) are placed in

a high impedance state when the device is deselected (CE₁

HIGH or CE₂LOW), the outputs are disabled (OE HIGH), or

during a write operation (CE₁LOW and CE₂HIGH and WE

LOW).

The CY62138F device is suitable for interfacing with processors

that have TTL I/P levels. It is not suitable for processors that

require CMOS I/P levels. Please see Electrical Characteristics

on page 4 for more details and suggested alternatives.

Logic Block Diagram

Cypress Semiconductor Corporation

Document Number: 001-13194 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 4, 2013

12 3 4 5 6 7...16

中文翻译

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与CY62138F_13相关器件

型号	品牌	获取价格	描述	数据表
CY62138FLL	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138FLL-45SXI	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138FLL-45SXI	INFINEON	获取价格	Asynchronous SRAM
CY62138FLL-45SXIT	INFINEON	获取价格	Asynchronous SRAM
CY62138FLL-45ZSXI	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138FLL-45ZSXIT	CYPRESS	获取价格	Standard SRAM, 256KX8, 45ns, CMOS, PDSO32
CY62138FV30	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138FV30_09	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138FV30_10	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138FV30_11	CYPRESS	获取价格	2-Mbit (256 K x 8) Static RAM Automatic power down when deselected

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