Datasheet > CY62138EV30LL-45BVXI

CY62138EV30LL-45BVXI

更新时间： 2024-11-25 14:56:15

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
17页	471K
描述
Asynchronous SRAM

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中文翻译

获取价格

数据手册

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CY62138EV30LL-45BVXI 数据手册

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CY62138EV30 MoBL^®

2-Mbit (256 K × 8) Static RAM

2-Mbit (256

K × 8) Static RAM

Features

Functional Description

■ Very high speed: 45 ns

❐ Wide voltage range: 2.20 V to 3.60 V

The CY62138EV30 is a high performance CMOS static RAM

organized as 256K words by eight bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption. The device can be put into standby mode reducing

power consumption when deselected (CE HIGH).

■ Pin compatible with CY62138CV30

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 7 A

■ Ultra low active power

❐ Typical active current: 2 mA at f = 1 MHz

Writing to the device is accomplished by taking Chip Enable (CE)

and Write Enable (WE) inputs LOW. Data on the eight I/O pins

(I/O₀through I/O₇) is then written into the location specified on

the address pins (A₀through A₁₈).

■ Easy memory expansion with CE and OE features

■ Automatic power down when deselected

Reading from the device is accomplished by taking Chip Enable

(CE) and Output Enable (OE) LOW while forcing Write Enable

(WE) HIGH. Under these conditions, the contents of the memory

location specified by the address pins appear on the I/O pins.

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

■ Offered in Pb-free 36-ball ball grid array (BGA) package

The eight input and output pins (I/O₀through I/O₇) are placed in

a high impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW and WE LOW).

For a complete list of related documentation, click here.

Logic Block Diagram

I/O

Data in Drivers

A₀

A₁

A²₃

A₄

A⁵

256K x 8

ARRAY

A⁶

A₈⁷

A₉

A₁₀

A₁₁

POWER

DOWN

COLUMN

DECODER

I/O

Cypress Semiconductor Corporation

Document Number: 38-05577 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 20, 2015

12 3 4 5 6 7...17

中文翻译

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与CY62138EV30LL-45BVXI相关器件

型号	品牌	获取价格	描述	数据表
CY62138EV30LL-45BVXI_12	CYPRESS	获取价格	2-Mbit (256 K Ã 8) MoBL Static RAM
CY62138EV30LL-45BVXIT	CYPRESS	获取价格	Standard SRAM, 256KX8, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62138EV30LL-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62138F	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138F_09	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138F_10	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138F_11	CYPRESS	获取价格	2-Mbit (256 K x 8) Static RAM Automatic power down when deselected
CY62138F_13	CYPRESS	获取价格	2-Mbit (256 K x 8) Static RAM
CY62138FLL	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138FLL-45SXI	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM

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