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CDC2509APWR PDF预览

CDC2509APWR

更新时间： 2024-11-20 03:25:07
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 257K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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中文翻译

获取价格

CDC2509APWR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP24,.25
针数：24Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.8
Is Samacsys：N系列：2509
输入调节：STANDARDJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：7.8 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.012 A
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：24
实输出次数：9最高工作温度：70 °C
最低工作温度：输出特性：SERIES-RESISTOR
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP24,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.2 ns座面最大高度：1.2 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
最小 fmax：100 MHzBase Number Matches：1

CDC2509APWR 数据手册

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SCAS603C − APRIL 1998 − REVISED DECEMBER 2004  
PW PACKAGE  
(TOP VIEW)  
D
Use CDCVF2509A as a Replacement for  
this Device  
D
D
D
D
D
D
D
Spread Spectrum Clock Compatible  
100-MHz Maximum Frequency  
AGND  
CLK  
AV  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
V
2
CC  
CC  
Available in Plastic 24-Pin TSSOP  
1Y0  
1Y1  
1Y2  
GND  
GND  
1Y3  
V
3
CC  
2Y0  
2Y1  
GND  
GND  
2Y2  
2Y3  
4
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
5
6
Distributes One Clock Input to One Bank of  
Five and One Bank of Four Outputs  
7
8
Separate Output Enable for Each Output  
Bank  
1Y4  
9
V
10  
11  
12  
V
CC  
CC  
External Feedback (FBIN) Pin Is Used to  
Synchronize the Outputs to the Clock Input  
1G  
FBOUT  
2G  
FBIN  
D
D
D
On-Chip Series Damping Resistors  
No External RC Network Required  
Operates at 3.3-V V  
CC  
description  
The CDC2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL  
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.  
It is specifically designed for use with synchronous DRAMs. The CDC2509A operates at 3.3-V V  
integrated series-damping resistors that make it ideal for driving point-to-point loads.  
and provides  
CC  
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output  
signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can  
be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs  
switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low  
state.  
Unlike many products containing PLLs, the CDC2509A does not require external RC networks. The loop filter  
for the PLL is included on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuitry, the CDC2509A requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required, following power up and application  
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback  
signals. The PLL can be bypassed for test purposes by strapping AV  
to ground.  
CC  
The CDC2509A is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2001 − 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

中文翻译

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CDC2509APWR 替代型号

型号 品牌 替代类型 描述 数据表
CDCF2509PWR TI

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