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BUK7606-30 PDF预览

BUK7606-30

更新时间: 2024-11-22 22:32:31
品牌 Logo 应用领域
恩智浦 - NXP 晶体晶体管
页数 文件大小 规格书
8页 54K
描述
TrenchMOS transistor Standard level FET

BUK7606-30 数据手册

 浏览型号BUK7606-30的Datasheet PDF文件第2页浏览型号BUK7606-30的Datasheet PDF文件第3页浏览型号BUK7606-30的Datasheet PDF文件第4页浏览型号BUK7606-30的Datasheet PDF文件第5页浏览型号BUK7606-30的Datasheet PDF文件第6页浏览型号BUK7606-30的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Standard level FET  
BUK7606-30  
GENERAL DESCRIPTION  
QUICK REFERENCE DATA  
N-channel enhancement mode  
standard level field-effect power  
transistor in a plastic envelope  
suitable for surface mounting using  
trench’ technology. The device  
features very low on-state resistance  
and has integral zener diodes giving  
ESD protection up to 2kV. It is  
intended for use in automotive and  
SYMBOL  
PARAMETER  
MAX.  
UNIT  
VDS  
ID  
Ptot  
Tj  
Drain-source voltage  
Drain current (DC)  
Total power dissipation  
Junction temperature  
Drain-source on-state  
30  
75  
188  
175  
6
V
A
W
˚C  
m  
RDS(ON)  
resistance  
VGS = 10 V  
general  
purpose  
switching  
applications.  
PINNING - SOT404  
PIN CONFIGURATION  
SYMBOL  
PIN  
1
DESCRIPTION  
d
mb  
gate  
2
drain  
source  
g
3
2
mb drain  
s
1
3
LIMITING VALUES  
Limiting values in accordance with the Absolute Maximum System (IEC 134)  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VDS  
VDGR  
±VGS  
ID  
ID  
IDM  
Drain-source voltage  
Drain-gate voltage  
Gate-source voltage  
Drain current (DC)  
-
-
-
-
-
-
-
-
30  
30  
20  
75  
53  
240  
188  
175  
V
V
V
A
A
A
W
˚C  
RGS = 20 kΩ  
-
Tmb = 25 ˚C  
Tmb = 100 ˚C  
Tmb = 25 ˚C  
Tmb = 25 ˚C  
-
Drain current (DC)  
Drain current (pulse peak value)  
Total power dissipation  
Storage & operating temperature  
Ptot  
Tstg, Tj  
- 55  
THERMAL RESISTANCES  
SYMBOL PARAMETER  
CONDITIONS  
TYP.  
MAX.  
UNIT  
Rth j-mb  
Rth j-a  
Thermal resistance junction to  
mounting base  
Thermal resistance junction to  
ambient  
-
-
0.8  
K/W  
minimum footprint, FR4  
board  
50  
-
K/W  
ESD LIMITING VALUE  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VC  
Electrostatic discharge capacitor  
voltage, all pins  
Human body model  
(100 pF, 1.5 k)  
-
2
kV  
December 1997  
1
Rev 1.100  

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