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74VCX16722MTD PDF预览

74VCX16722MTD

更新时间: 2024-11-05 22:45:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
8页 85K
描述
Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs

74VCX16722MTD 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP64,.32,20
针数:64Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.66
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G64
JESD-609代码:e3长度:17 mm
负载电容(CL):30 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:2
位数:22功能数量:1
端口数量:2端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP64,.32,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:RAIL
峰值回流温度(摄氏度):260电源:3.3 V
传播延迟(tpd):9.2 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:6.1 mmBase Number Matches:1

74VCX16722MTD 数据手册

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February 1999  
Revised July 2000  
74VCX16722  
Low Voltage 22-Bit Register  
with 3.6V Tolerant Inputs and Outputs  
General Description  
Features  
1.65V–3.6V VCC specifications provided  
The VCX16722 low voltage 22-bit register contains twenty-  
two non-inverting D-type flip-flops with 3-STATE outputs  
and is intended for bus oriented applications. The design  
has been optimized for use with JEDEC compliant 200 pin  
DIMM modules.  
3.6V tolerant inputs and outputs  
tPD (CLK to On)  
3.6ns max for 3.0V to 3.6V VCC  
4.6ns max for 2.3V to 2.7V VCC  
9.2ns max for 1.65V to 1.95V VCC  
The 74VCX16722 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O capability up to 3.6V.  
Power-down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
Meets JEDEC registered module specifications  
The 74VCX16722 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Static Drive (IOH/IOL  
)
±24mA @ 3.0V  
±18mA @ 2.3V  
±6mA @ 1.65V  
Latchup performance exceeds 300 mA  
ESD performance:  
Human body model > 2000V  
Machine model >200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pull-up resistor; the minimum  
value of the resistor is determined by the current sourcing capability of the  
driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74VCX16722MTD  
MTD64  
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
© 2000 Fairchild Semiconductor Corporation  
DS500192  
www.fairchildsemi.com  

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