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74VCX16839MTD

更新时间： 2024-09-15 22:26:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
7页 64K
描述
Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs

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74VCX16839MTD 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：6.10 MM, MO-153, TSSOP-56
针数：56Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.45
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e3长度：14 mm
逻辑集成电路类型：BUS DRIVER湿度敏感等级：2
位数：20功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V传播延迟（tpd）：8.8 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

74VCX16839MTD 数据手册

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July 1997  
Revised April 1999  
74VCX16839  
Low Voltage 20-Bit Selectable Register/Buffer with 3.6V  
Tolerant Inputs and Outputs  
General Description  
Features  
■ Compatible with PC100 and PC133 DIMM module  
The VCX16839 contains twenty non-inverting selectable  
buffered or registered paths. The device can be configured  
to operate in a registered, or flow through buffer mode by  
utilizing the register enable (REGE) and Clock (CP) sig-  
nals. The device operates in a 20-bit word wide mode. All  
outputs can be placed into 3-STATE through use of the OE  
pin. These devices are ideally suited for buffered or regis-  
tered 168 pin and 200 pin SDRAM DIMM memory mod-  
ules.  
specifications  
■ 1.65V–3.6V VCC supply operation  
■ 3.6V tolerant inputs and outputs  
■ tPD (CP to On)  
3.2 ns max for 3.0V to 3.6V VCC  
4.4 ns max for 2.3V to 2.7V VCC  
8.8 ns max for 1.65V to 1.95V VCC  
The 74VCX16839 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O compatibility up to 3.6V.  
■ Power-off high impedance inputs and outputs  
■ Supports live insertion and withdrawal (Note 1)  
The 74VCX16839 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
■ Static Drive (IOH/IOL  
)
±24 mA @ 3.0V VCC  
±18 mA @ 2.3V VCC  
±6 mA @ 1.65V VCC  
■ Uses patented noise/EMI reduction circuitry  
■ Latch-up performance exceeds 300 mA  
■ ESD performance:  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to V  
through a pull-up resistor; the minimum  
CC  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number Package Number  
Package Descriptions  
74VCX16839MTD  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
OE  
Description  
Output Enable Input (Active LOW)  
Inputs  
I0–I19  
O0–O19  
CP  
Outputs  
Clock Pulse Input  
Register Enable Input  
REGE  
© 1999 Fairchild Semiconductor Corporation  
DS500105.prf  
www.fairchildsemi.com  
1234567

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