Datasheet > 74VCX16835MTDX

74VCX16835MTDX

更新时间： 2024-09-15 23:24:35

品牌	Logo	应用领域
其他 - ETC		驱动器逻辑集成电路光电二极管
页数	文件大小	规格书
10页	98K
描述
18-Bit Buffer/Driver

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数据手册

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74VCX16835MTDX 数据手册

October 1998

Revised August 2001

74VCX16835

Low Voltage 18-Bit Universal Bus Driver

with 3.6V Tolerant Inputs and Outputs

General Description

The VCX16835 low voltage 18-bit universal bus driver

combines D-type latches and D-type flip-flops to allow data

flow in transparent, latched and clocked modes.

Features

■ Compatible with PC100 DIMM module specifications

■ 1.65V–3.6V V_CCsupply operation

■ 3.6V tolerant inputs and outputs

■ t_PD(CLK to O_n)

Data flow is controlled by output-enable (OE), latch-enable

(LE), and clock (CLK) inputs. The device operates in

Transparent Mode when LE is held HIGH. The device

operates in clocked mode when LE is LOW and CLK is tog-

gled. Data transfers from the Inputs (I_n) to Ouputs (O_n) on a

4.2ns max for 3.0V to 3.6V V_CC

5.2ns max for 2.3V to 2.7V V_CC

9.2ns max for 1.65V to 1.95V V_CC

Positive Edge Transition of the Clock. When OE is LOW,

the output data is enabled. When OE is HIGH the output

port is in a high impedance state.

■ Power-down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■ Static Drive (I_OH/I_OL

)

The 74VCX16835 is designed for low voltage (1.65V to

3.6V) V_CCapplications with I/O capability up to 3.6V.

±24mA @ 3.0V

±18mA @ 2.3V

±6mA @ 1.65V

The 74VCX16835 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

■ Latchup performance exceeds 300 mA

■ ESD performance:

Human body model > 2000V

Machine model >200V

■ Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V_CC(OE to GND) through a pulldown resistor;

the minimum value of the resistor is determined by the current sourcing

capability of the driver.

Ordering Code:

Order Number

Package Number

Package Description

74VCX16835GX

(Note 2)

BGA54A

(Preliminary)

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

74VCX16835MTD

(Note 3)

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Note 2: BGA package available in Tape and Reel only.

Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

DS500173

www.fairchildsemi.com

12 3 4 5 6 7...10

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与74VCX16835MTDX相关器件

型号	品牌	获取价格	描述	数据表
74VCX16838	FAIRCHILD	获取价格	Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
74VCX16838_05	FAIRCHILD	获取价格	Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
74VCX16838MTD	FAIRCHILD	获取价格	Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
74VCX16838MTDX	FAIRCHILD	获取价格	Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
74VCX16839	FAIRCHILD	获取价格	Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
74VCX16839MTD	FAIRCHILD	获取价格	Low Voltage 20-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
74VCX16839MTDX	ETC	获取价格	Buffer/Flip-Flop
74VCX16839MTDX_NL	FAIRCHILD	获取价格	Bus Driver, ALVC/VCX/A Series, 1-Func, 20-Bit, True Output, CMOS, PDSO56, 6.10 MM, MO-153,
74VCX16841	FAIRCHILD	获取价格	Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
74VCX16841_04	FAIRCHILD	获取价格	Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs

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