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74VCX16821MEA PDF预览

74VCX16821MEA

更新时间: 2024-11-06 19:30:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 65K
描述
Bus Driver, ALVC/VCX/A Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56

74VCX16821MEA 技术参数

生命周期:Obsolete包装说明:SSOP,
Reach Compliance Code:unknown风险等级:5.83
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G56
长度:18.415 mm逻辑集成电路类型:BUS DRIVER
位数:10功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
传播延迟(tpd):8.8 ns认证状态:Not Qualified
座面最大高度:2.74 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.65 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

74VCX16821MEA 数据手册

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March 1998  
Revised April 1999  
74VCX16821  
Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant  
Inputs and Outputs  
General Description  
The VCX16821 contains twenty non-inverting D-type flip-  
flops with 3-STATE outputs and is intended for bus oriented  
applications.  
Features  
1.65V–3.6V VCC supply operation  
3.6V tolerant inputs and outputs  
tPD  
The 74VCX16821 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O compatibility up to 3.6V.  
3.5 ns max for 3.0V to 3.6V VCC  
4.4 ns max for 2.3V to 2.7V VCC  
8.8 ns max for 1.65V to 1.95V VCC  
The 74VCX16821 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Power-off high impedance inputs and outputs  
Supports live insertion and withdrawal (Note 1)  
Static Drive (IOH/IOL  
)
±24 mA @ 3.0V VCC  
±18 mA @ 2.3V VCC  
±6 mA @ 1.65V VCC  
Uses patented noise/EMI reduction circuitry  
Latch-up performance exceeds 300 mA  
ESD performance:  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to V  
through a pull-up resistor; the minimum  
CC  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number Package Number  
Package Descriptions  
74VCX16821MTD  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
OEn  
Description  
Output Enable Input (Active LOW)  
Clock Input  
CLKn  
D0–D19  
O0–O19  
Inputs  
Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS500130.prf  
www.fairchildsemi.com  

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