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74VCX16827 PDF预览

74VCX16827

更新时间: 2024-11-05 22:45:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
7页 58K
描述
Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs

74VCX16827 数据手册

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March 1998  
Revised April 1999  
74VCX16827  
Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant  
Inputs and Outputs  
General Description  
The VCX16827 contains twenty non-inverting buffers with  
Features  
1.65V–3.6V VCC supply operation  
3-STATE outputs to be employed as  
a memory and  
3.6V tolerant inputs and outputs  
tPD  
address driver, clock driver, or bus oriented transmitter/  
receiver carrying parity. The device is byte controlled. Each  
byte has NOR output enables for maximum control flexibil-  
ity.  
2.5 ns max for 3.0V to 3.6V VCC  
3.0 ns max for 2.3V to 2.7V VCC  
6.0 ns max for 1.65V to 1.95V VCC  
The 74VCX16827 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O capability up to 3.6V.  
Power-off high impedance inputs and outputs  
Supports live insertion and withdrawal (Note 1)  
The 74VCX16827 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Static Drive (IOH/IOL  
)
±24 mA @ 3.0V VCC  
±18 mA @ 2.3V VCC  
±6 mA @ 1.65V VCC  
Uses patented noise/EMI reduction circuitry  
Latch-up performance exceeds 300 mA  
ESD performance:  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to V  
through a pull-up resistor; the minimum  
CC  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74VCX16827MTD  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
OEn  
Description  
Output Enable Input (Active LOW)  
Inputs  
I0–I19  
O0–O19  
Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS500131.prf  
www.fairchildsemi.com  

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