Datasheet > 74LVC1G386GV

74LVC1G386GV

更新时间： 2024-11-18 11:09:51

品牌	Logo	应用领域
安世 - NEXPERIA		栅光电二极管逻辑集成电路石英晶振触发器
页数	文件大小	规格书
12页	210K
描述
3-input EXCLUSIVE-OR gateProduction

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74LVC1G386GV 数据手册

74LVC1G386

3-input EXCLUSIVE-OR gate

Rev. 5 — 1 February 2022

Product data sheet

1. General description

The 74LVC1G386 is a single 3-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V

or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V

environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

•

Wide supply voltage range from 1.65 V to 5.5 V

•

Overvoltage tolerant inputs to 5.5 V

High noise immunity

CMOS low power dissipation

Direct interface with TTL levels

±24 mA output drive (V_CC= 3.0 V)

I_OFFcircuitry provides partial Power-down mode operation

Latch-up performance exceeds 250 mA

Complies with JEDEC standard:

•

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

JESD36 (4.5 V to 5.5 V)

•

ESD protection:

•

HBM EIA/JESD22-A114E exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

Specified from -40 to +85 °C and -40 to +125 °C.

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC1G386GW

74LVC1G386GV

-40 °C to +125 °C

TSSOP6

plastic thin shrink small outline package;

6 leads; body width 1.25 mm

SOT363-2

-40 °C to +125 °C

SC-74; TSOP6

plastic surface-mounted package; 6 leads

SOT457

12 3 4 5 6 7...12

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