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74GTL16923DGGRE4

更新时间： 2024-09-09 06:31:51
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德州仪器 - TI 总线收发器
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13页 183K
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18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER

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74GTL16923DGGRE4 数据手册

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SN74GTL16923  
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER  
www.ti.com  
SCBS674G–AUGUST 1996–REVISED APRIL 2005  
FEATURES  
DGG PACKAGE  
(TOP VIEW)  
•
•
•
•
•
Member of the Texas Instruments Widebus™  
Family  
CEAB  
1A1  
CLKAB  
1OEAB  
1
2
3
4
5
6
7
8
9
64  
63  
OEC™ Circuitry Improves Signal Integrity and  
Reduces Electromagnetic Interference  
GND  
1A2  
62 1OEBA  
D-Type Flip-Flops With Qualified Storage  
Enable  
1B1  
GND  
1B2  
1B3  
61  
60  
59  
58  
57  
1A3  
Translates Between GTL/GTL+ Signal Levels  
and LVTTL Logic Levels  
GND  
V
CC  
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltages With  
1A4  
V
CC  
GND  
56 1B4  
55 1B5  
3.3-V VCC  
)
1A5 10  
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
1A6  
GND  
1A7  
1B6  
GND  
1B7  
11  
12  
13  
54  
53  
52  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors on  
A Port  
1A8 14  
GND 15  
1A9 16  
2A1 17  
51 1B8  
50 GND  
49 1B9  
48 2B1  
•
•
•
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
GND  
GND  
18  
47  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
2A2 19  
2A3 20  
GND 21  
2A4 22  
2A5 23  
GND 24  
2A6 25  
46 2B2  
45 2B3  
44 GND  
43 2B4  
42 2B5  
41 2B6  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
40  
V
REF  
DESCRIPTION/ORDERING INFORMATION  
V
26  
39 2B7  
38 2B8  
37 GND  
36 2B9  
CC  
GND 27  
2A7 28  
2A8 29  
The SN74GTL16923 is an 18-bit registered bus  
transceiver that provides LVTTL-to-GTL/GTL+ and  
GTL/GTL+-to-LVTTL signal-level translation. This  
device is partitioned as two 9-bit transceivers with  
individual output-enable controls and contains D-type  
flip-flops for temporary storage of data flowing in  
either direction. This device provides an interface  
between cards operating at LVTTL logic levels and a  
backplane operating at GTL/GTL+ signal levels.  
Higher-speed operation is a direct result of the  
reduced output swing (<1 V), reduced input threshold  
levels, and OEC™ circuitry.  
30  
31  
35  
34  
GND  
2A9  
CEBA 32  
2OEBA  
2OEAB  
33 CLKBA  
<br/>  
The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred  
higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative  
of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or  
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels. All inputs can be  
driven from either 3.3-V or 5-V devices, which allows use in a mixed 3.3-V/5-V system environment. VREF is the  
reference input voltage for the B port.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, OEC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1996–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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