5秒后页面跳转
捷配首页

Datasheet > 74GTLP2033DGGRG4
74GTLP2033DGGRG4 PDF预览

74GTLP2033DGGRG4

更新时间： 2024-09-09 14:48:03
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
20页 589K
描述
GTLP SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48

阅读下载

中文翻译

获取价格

74GTLP2033DGGRG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：GREEN, PLASTIC, TSSOP-48针数：48
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.73Is Samacsys：N
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：GTLPJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：12.5 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.1 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：OPEN-DRAIN/3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：7.4 ns
传播延迟（tpd）：8.8 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.45 V最小供电电压 (Vsup)：3.15 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：GTL/P & LVTTL
触发器类型：POSITIVE EDGE宽度：6.1 mm
Base Number Matches：1

74GTLP2033DGGRG4 数据手册

 浏览型号74GTLP2033DGGRG4的Datasheet PDF文件第2页浏览型号74GTLP2033DGGRG4的Datasheet PDF文件第3页浏览型号74GTLP2033DGGRG4的Datasheet PDF文件第4页浏览型号74GTLP2033DGGRG4的Datasheet PDF文件第5页浏览型号74GTLP2033DGGRG4的Datasheet PDF文件第6页浏览型号74GTLP2033DGGRG4的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄ ꢅꢆꢇ ꢈꢉ ꢊꢊ  
ꢋ ꢌꢍꢎ ꢅ ꢆꢏ ꢅꢅ ꢆꢌꢅꢐ ꢌꢄꢅ ꢆꢇ ꢑꢒꢓ ꢔꢀ ꢅꢑꢍꢆ ꢕꢌꢕ ꢒꢄ ꢕꢌꢖꢑꢅ ꢕ ꢖꢕ ꢄꢎ ꢀꢅ ꢕꢖꢕꢒ ꢅ ꢖꢑꢁ ꢀꢗ ꢕ ꢎꢏ ꢕ ꢖ  
ꢘ ꢎꢅ ꢙ ꢀꢇ ꢆꢎ ꢅ ꢆꢏꢅ ꢅ ꢆ ꢇꢐ ꢖꢅ ꢑꢁꢒ ꢚ ꢕꢕꢒ ꢍꢑ ꢗꢛ ꢇ ꢑ ꢅ ꢙ  
SCES352C − JUNE 2001 − REVISED SEPTEMBER 2001  
DGG OR DGV PACKAGE  
(TOP VIEW)  
D
D
D
D
D
Member of the Texas Instruments  
WidebusFamily  
TI-OPCCircuitry Limits Ringing on  
Unevenly Loaded Backplanes  
IMODE1  
IMODE0  
BIAS V  
B1  
GND  
OEAB  
B2  
ERC  
OEAB  
B3  
1
2
3
4
5
6
7
8
9
48  
47  
46  
45  
44  
43  
42  
41  
40  
AI1  
AO1  
GND  
AI2  
CC  
OECCircuitry Improves Signal Integrity  
and Reduces Electromagnetic Interference  
Bidirectional Interface Between GTLP  
Signal Levels and LVTTL Logic Levels  
AO2  
V
Split LVTTL Port Provides a Feedback Path  
for Control and Diagnostics Monitoring  
CC  
AI3  
AO3  
D
LVTTL Interfaces Are 5-V Tolerant  
GND 10  
39 GND  
D
High-Drive GTLP Open-Drain Outputs  
(100 mA)  
AI4  
AO4  
CLKAB/LEAB  
B4  
11  
12  
38  
37  
D
D
LVTTL Outputs (−24 mA/24 mA)  
AO5 13  
AI5 14  
36 B5  
Variable Edge-Rate Control (ERC) Input  
Selects GTLP Rise and Fall Times for  
Optimal Data-Transfer Rate and Signal  
Integrity in Distributed Loads  
35 CLKBA/LEBA  
34 GND  
GND 15  
AO6 16  
AI6 17  
33 B6  
32 OEBA  
V
18  
31  
V
D
D
D
D
I
, Power-Up 3-State, and BIAS V  
CC  
CC  
off CC  
AO7 19  
30 B7  
Support Live Insertion  
AI7 20  
29 LOOPBACK  
28 GND  
27 B8  
Distributed V and GND Pins Minimize  
High-Speed Switching Noise  
CC  
GND 21  
AO8 22  
AI8 23  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
26  
V
REF  
25 OMODE1  
OMODE0 24  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 1000-V Charged-Device Model (C101)  
description  
The SN74GTLP2033 is a high-drive, 8-bit, three-wire registered transceiver that provides inverted  
LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and  
flip-flop modes of data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback  
path for control and diagnostics monitoring, the same functionality as the SN74FB2033. The device provides  
a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal  
levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result  
of GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC  
circuitry, and TI-OPCcircuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have  
been designed and tested using several backplane models. The high drive allows incident-wave switching in  
heavily loaded backplanes with equivalent load impedance down to 11 Ω.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.  
ꢇ
ꢇ
ꢖ
ꢐ
ꢫ
ꢒ
ꢦ
ꢔ
ꢗ
ꢤ
ꢅ
ꢥ
ꢎ
ꢟ
ꢐ
ꢝ
ꢁ
ꢞ
ꢒ
ꢑ
ꢅ
ꢑ
ꢜ
ꢝ
ꢧ
ꢞ
ꢟ
ꢥ
ꢠ
ꢡ
ꢢ
ꢢ
ꢣ
ꢣ
ꢜ
ꢜ
ꢟ
ꢟ
ꢝ
ꢝ
ꢜ
ꢤ
ꢤ
ꢨ
ꢥ
ꢦ
ꢠ
ꢠ
ꢧ
ꢧ
ꢝ
ꢣ
ꢢ
ꢡ
ꢤ
ꢤ
ꢟ
ꢞ
ꢨ
ꢅꢧ  
ꢦ
ꢩ
ꢤ
ꢪ
ꢜ
ꢥ
ꢢ
ꢤ
ꢣ
ꢜ
ꢣ
ꢟ
ꢠ
ꢝ
ꢦ
ꢫ
ꢢ
ꢝ
ꢣ
ꢣ
ꢧ
ꢤ
ꢬ
Copyright 2001, Texas Instruments Incorporated  
ꢠ
ꢟ
ꢥ
ꢣ
ꢟ
ꢠ
ꢡ
ꢣ
ꢟ
ꢤ
ꢨ
ꢜ
ꢞ
ꢜ
ꢥ
ꢧ
ꢠ
ꢣ
ꢭ
ꢣ
ꢧ
ꢠ
ꢟ
ꢞ
ꢮ
ꢢ
ꢎ
ꢝ
ꢡ
ꢧ
ꢤ
ꢣ
ꢢ
ꢝ
ꢫ
ꢢ
ꢠ
ꢫ
ꢯ
ꢢ
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
ꢠ
ꢠ
ꢢ
ꢝ
ꢣ
ꢰ
ꢬ
ꢇ
ꢠ
ꢟ
ꢫ
ꢦ
ꢥ
ꢣ
ꢜ
ꢟ
ꢝ
ꢨ
ꢠ
ꢟ
ꢥ
ꢧ
ꢤ
ꢤ
ꢜ
ꢝ
ꢱ
ꢫ
ꢟ
ꢧ
ꢤ
ꢝ
ꢟ
ꢣ
ꢝ
ꢧ
ꢥ
ꢧ
ꢤ
ꢤ
ꢢ
ꢠ
ꢜ
ꢪ
ꢰ
ꢜ
ꢝ
ꢥ
ꢪ
ꢦ
ꢫ
ꢧ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...20

中文翻译

下载PDF

与74GTLP2033DGGRG4相关器件

型号 品牌 获取价格 描述 数据表
74GTLP2033DGVRE4 TI

获取价格

 		8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND
74GTLP2033DGVRG4 TI

获取价格

 		IC GTLP SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO48, GREEN, PLASTIC, TVS
74GTLP2034DGGRE4 TI

获取价格

 		8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND
74GTLP2034DGVRE4 TI

获取价格

 		8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND
74GTLP22033DGGRE4 TI

获取价格

 		8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND
74GTLP22033DGGRG4 TI

获取价格

 		8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND
74GTLP22033DGVRG4 TI

获取价格

 		GTLP SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO48, GREEN, PLASTIC, TVSOP-
74GTLP22034DGGRE4 TI

获取价格

 		8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND
74GTLP22034DGGRG4 TI

获取价格

 		IC GTLP SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-4
74GTLP22034DGVRE4 TI

获取价格

 		8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND

与74GTLP2033DGGRG4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证