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74GTLPH16916VRG4 PDF预览

74GTLPH16916VRG4

更新时间： 2024-09-14 17:32:35
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器电视
页数 文件大小 规格书
18页 384K
描述
GTLP SERIES, 17-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TVSOP-56

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74GTLPH16916VRG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SSOP包装说明：GREEN, PLASTIC, TVSOP-56
针数：56Reach Compliance Code：unknown
风险等级：5.84控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：GTLP
JESD-30 代码：R-PDSO-G56长度：11.3 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.05 A
位数：17功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.25,16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
最大电源电流（ICC）：50 mAProp。Delay @ Nom-Sup：6 ns
传播延迟（tpd）：6.3 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.45 V最小供电电压 (Vsup)：3.15 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：GTLP & LVTTL触发器类型：POSITIVE EDGE
宽度：4.4 mmBase Number Matches：1

74GTLPH16916VRG4 数据手册

 浏览型号74GTLPH16916VRG4的Datasheet PDF文件第2页浏览型号74GTLPH16916VRG4的Datasheet PDF文件第3页浏览型号74GTLPH16916VRG4的Datasheet PDF文件第4页浏览型号74GTLPH16916VRG4的Datasheet PDF文件第5页浏览型号74GTLPH16916VRG4的Datasheet PDF文件第6页浏览型号74GTLPH16916VRG4的Datasheet PDF文件第7页 
SN74GTLPH16916  
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER  
WITH BUFFERED CLOCK OUTPUTS  
www.ti.com  
SCES347C–JANUARY 2001–REVISED JANUARY 2006  
FEATURES  
DGG OR DGV PACKAGE  
•
Member of the Texas Instruments Widebus™  
(TOP VIEW)  
Family  
OEAB  
LEAB  
A1  
GND  
A2  
CEAB  
CLKAB  
54 B1  
1
2
3
4
5
6
7
8
9
56  
55  
•
UBT™ Transceiver Combines D-Type Latches  
and D-Type Flip-Flops for Operation in  
Transparent, Latched, Clocked, and  
Clock-Enabled Modes  
TI-OPC™ Circuitry Limits Ringing on  
Unevenly Loaded Backplanes  
OEC™ Circuitry Improves Signal Integrity and  
Reduces Electromagnetic Interference  
Bidirectional Interface Between GTLP Signal  
Levels and LVTTL Logic Levels  
GTLP Buffered CLKAB Signal (CLKOUT)  
LVTTL Interfaces Are 5-V Tolerant  
Medium-Drive GTLP Outputs (50 mA)  
LVTTL Outputs (–24 mA/24 mA)  
GTLP Rise and Fall Times Designed for  
Optimal Data-Transfer Rate and Signal  
Integrity in Distributed Loads  
GND  
B2  
B3  
BIAS V  
53  
52  
51  
50  
•
•
•
A3  
V
CC  
CC  
A4  
A5  
A6 10  
GND  
A7  
A8  
A9 14  
A10 15  
A11 16  
A12 17  
49 B4  
48 B5  
47 B6  
GND  
B7  
B8  
11  
12  
13  
46  
45  
44  
•
•
•
•
•
43 B9  
42 B10  
41 B11  
40 B12  
GND  
GND  
18  
39  
A13 19  
A14 20  
A15 21  
38 B13  
37 B14  
36 B15  
•
Ioff, Power-Up 3-State, and BIAS VCC Support  
Live Insertion  
•
•
Bus Hold on A-Port Data Inputs  
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
V
22  
35  
V
REF  
CC  
A16 23  
A17 24  
34 B16  
33 B17  
32 GND  
31 CLKOUT  
30 CLKBA  
29 CEBA  
GND 25  
CLKIN 26  
OEBA 27  
LEBA 28  
•
•
– 1000-V Charged-Device Model (C101)  
DESCRIPTION  
The SN74GTLPH16916 is a medium-drive, 17-bit UBT™ transceiver that provides LVTTL-to-GTLP and  
GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes of  
data transfer. Additionally, it provides for a copy of CLKAB at GTLP signal levels (CLKOUT) and conversion of a  
GTLP clock to LVTTL logic levels (CLKIN). The device provides a high-speed interface between cards operating  
at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster  
than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V),  
reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved  
GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several  
backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with  
equivalent load impedance down to 19 Ω.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, UBT, TI-OPC, OEC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2001–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...18

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