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74GTLPH16945GRG4 PDF预览

74GTLPH16945GRG4

更新时间： 2024-09-14 19:15:23
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
16页 470K
描述
GTLP SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48

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74GTLPH16945GRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP48,.3,20针数：48
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.73其他特性：WITH DIRECTION CONTROL
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：GTLPJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：12.5 mm
逻辑集成电路类型：BUS TRANSCEIVER最大I（ol）：0.05 A
湿度敏感等级：1位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：50 mA
传播延迟（tpd）：6.3 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.45 V最小供电电压 (Vsup)：3.15 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：GTL/P & LVTTL
宽度：6.1 mmBase Number Matches：1

74GTLPH16945GRG4 数据手册

 浏览型号74GTLPH16945GRG4的Datasheet PDF文件第2页浏览型号74GTLPH16945GRG4的Datasheet PDF文件第3页浏览型号74GTLPH16945GRG4的Datasheet PDF文件第4页浏览型号74GTLPH16945GRG4的Datasheet PDF文件第5页浏览型号74GTLPH16945GRG4的Datasheet PDF文件第6页浏览型号74GTLPH16945GRG4的Datasheet PDF文件第7页 
SN74GTLPH16945  
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER  
www.ti.com  
SCES292D–OCTOBER 1999–REVISED JUNE 2005  
FEATURES  
DGG OR DGV PACKAGE  
(TOP VIEW)  
•
•
•
•
Member of the Texas Instruments Widebus™  
Family  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1DIR  
1A1  
1A2  
GND  
1A3  
1A4  
1OE  
1B1  
1B2  
GND  
1B3  
1B4  
BIAS V  
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
TI-OPC™ Circuitry Limits Ringing on  
Unevenly Loaded Backplanes  
2
3
OEC™ Circuitry Improves Signal Integrity and  
Reduces Electromagnetic Interference  
4
5
Bidirectional Interface Between GTLP Signal  
Levels and LVTTL Logic Levels  
6
7
V
CC  
CC  
•
•
•
•
LVTTL Interfaces Are 5-V Tolerant  
Medium-Drive GTLP Outputs (50 mA)  
LVTTL Outputs (–24 mA/24 mA)  
8
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
GTLP Rise and Fall Times Designed for  
Optimal Data-Transfer Rate and Signal  
Integrity in Distributed Loads  
•
Ioff, Power-Up 3-State, and BIAS VCC Support  
Live Insertion  
•
•
Bus Hold on A-Port Data Inputs  
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
V
CC  
V
REF  
2A5  
2A6  
GND  
2A7  
2A8  
2DIR  
2B5  
2B6  
GND  
2B7  
2B8  
2OE  
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
DESCRIPTION/ORDERING INFORMATION  
The SN74GTLPH16945 is a medium-drive, 16-bit bus transceiver that provides LVTTL-to-GTLP and  
GTLP-to-LVTTL signal-level translation. It is partitioned as two 8-bit transceivers. The device provides a  
high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal  
levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result  
of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™  
circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have  
been designed and tested using several backplane models. The medium drive allows incident-wave switching in  
heavily loaded backplanes with equivalent load impedance down to 19 Ω.  
GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard  
JESD 8-3. The ac specification of the SN74GTLPH16945 is given only at the preferred higher noise margin  
GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP  
(VTT = 1.5 V and VREF = 1 V) signal levels.  
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,  
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input  
reference voltage.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, TI-OPC, OEC, TI are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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