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74GTLPH1616DGGRE4 PDF预览

74GTLPH1616DGGRE4

更新时间： 2024-09-09 12:50:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件时钟
页数 文件大小 规格书
18页 351K
描述
17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS

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74GTLPH1616DGGRE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP64,.32,20针数：64
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.84控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：GTLP
JESD-30 代码：R-PDSO-G64JESD-609代码：e4
长度：17 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.1 A湿度敏感等级：1
位数：17功能数量：1
端口数量：2端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP64,.32,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：45 mAProp。Delay @ Nom-Sup：7.1 ns
传播延迟（tpd）：7.6 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.45 V最小供电电压 (Vsup)：3.15 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：GTLP & LVTTL
触发器类型：POSITIVE EDGE宽度：6.1 mm
Base Number Matches：1

74GTLPH1616DGGRE4 数据手册

 浏览型号74GTLPH1616DGGRE4的Datasheet PDF文件第2页浏览型号74GTLPH1616DGGRE4的Datasheet PDF文件第3页浏览型号74GTLPH1616DGGRE4的Datasheet PDF文件第4页浏览型号74GTLPH1616DGGRE4的Datasheet PDF文件第5页浏览型号74GTLPH1616DGGRE4的Datasheet PDF文件第6页浏览型号74GTLPH1616DGGRE4的Datasheet PDF文件第7页 
SN74GTLPH1616  
17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER  
WITH BUFFERED CLOCK OUTPUTS  
www.ti.com  
SCES346C–JANUARY 2001–REVISED DECEMBER 2005  
FEATURES  
DGG PACKAGE  
•
Member of the Texas Instruments Widebus™  
(TOP VIEW)  
Family  
OEAB  
LEAB  
A1  
A2  
GND  
A3  
CEAB  
CLKAB  
B1  
B2  
GND  
B3  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
•
UBT™ Transceiver Combines D-Type Latches  
and D-Type Flip-Flops for Operation in  
Transparent, Latched, Clocked, or  
Clock-Enabled Modes  
2
3
4
5
•
•
•
TI-OPC™ Circuitry Limits Ringing on  
Unevenly Loaded Backplanes  
6
V
CC  
BIAS V  
7
CC  
OEC™ Circuitry Improves Signal Integrity and  
Reduces Electromagnetic Interference  
A4  
A5  
GND  
A6  
A7  
A8  
B4  
B5  
GND  
B6  
B7  
8
9
Bidirectional Interface Between GTLP Signal  
Levels and LVTTL Logic Levels  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
•
•
•
•
•
GTLP Buffered CLKAB Signal (CLKOUT)  
LVTTL Interfaces Are 5-V Tolerant  
High-Drive GTLP Outputs (100 mA)  
LVTTL Outputs (–24 mA/24 mA)  
B8  
GND  
A9  
GND  
B9  
V
CC  
V
CC  
Variable Edge-Rate Control (ERC) Input  
Selects GTLP Rise and Fall Times for Optimal  
Data-Transfer Rate and Signal Integrity in  
Distributed Loads  
A10  
GND  
A11  
A12  
GND  
A13  
A14  
GND  
A15  
B10  
GND  
B11  
B12  
GND  
B13  
B14  
GND  
B15  
•
Ioff, Power-Up 3-State, and BIAS VCC Support  
Live Insertion  
•
•
Bus Hold on A-Port Data Inputs  
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
V
CC  
V
REF  
•
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
A16  
ERC  
A17  
B16  
GND  
B17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
CLKIN 30  
OEBA 31  
35 CLKOUT  
34 CLKBA  
– 1000-V Charged-Device Model (C101)  
LEBA  
CEBA  
32  
33  
DESCRIPTION/ORDERING INFORMATION  
The SN74GTLPH1616 is  
a high-drive, 17-bit UBT™ transceiver that provides LVTTL-to-GTLP and  
GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, clocked, or clock-enabled  
modes of data transfer. Additionally, it provides for a copy of CLKAB at GTLP signal levels (CLKOUT) and  
conversion of a GTLP clock to LVTTL logic levels (CLKIN). The device provides a high-speed interface between  
cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three  
times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing  
(<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry.  
Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using  
several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with  
equivalent load impedance down to 11 Ω.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, UBT, TI-OPC, OEC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2001–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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