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74GTLPH1612DGGRE4

更新时间： 2024-09-09 03:07:43
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德州仪器 - TI 总线收发器
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15页 158K
描述
18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER

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74GTLPH1612DGGRE4 数据手册

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SN74GTLPH1612  
18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE  
UNIVERSAL BUS TRANSCEIVER  
www.ti.com  
SCES287D–OCTOBER 1999–REVISED MAY 2005  
FEATURES  
DGG PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
OEAB  
LEAB  
A1  
A2  
GND  
A3  
CEAB  
CLKAB  
B1  
B2  
GND  
B3  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
•
UBT™ Transceiver Combines D-Type Latches  
and D-Type Flip-Flops for Operation in  
Transparent, Latched, Clocked, or  
Clock-Enabled Modes  
2
3
4
5
•
•
•
TI-OPC™ Circuitry Limits Ringing on  
Unevenly Loaded Backplanes  
6
V
CC  
BIAS V  
7
CC  
OEC™ Circuitry Improves Signal Integrity and  
Reduces Electromagnetic Interference  
A4  
A5  
GND  
A6  
A7  
A8  
B4  
B5  
GND  
B6  
B7  
8
9
Bidirectional Interface Between GTLP Signal  
Levels and LVTTL Logic Levels  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
•
•
•
•
LVTTL Interfaces Are 5-V Tolerant  
High-Drive GTLP Outputs (100 mA)  
LVTTL Outputs (–24 mA/24 mA)  
B8  
GND  
A9  
GND  
B9  
Variable Edge-Rate Control (ERC) Input  
Selects GTLP Rise and Fall Times for Optimal  
Data-Transfer Rate and Signal Integrity in  
Distributed Loads  
V
CC  
V
CC  
A10  
GND  
A11  
A12  
GND  
A13  
A14  
GND  
A15  
B10  
GND  
B11  
B12  
GND  
B13  
B14  
GND  
B15  
•
Ioff, Power-Up 3-State, and BIAS VCC Support  
Live Insertion  
•
•
Bus Hold on A-Port Data Inputs  
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
•
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
V
CC  
V
REF  
A16  
ERC  
A17  
B16  
GND  
B17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
A18 30  
35 B18  
– 1000-V Charged-Device Model (C101)  
OEBA 31  
34 CLKBA  
LEBA  
CEBA  
32  
33  
DESCRIPTION  
The SN74GTLPH1612 is  
a high-drive, 18-bit UBT™ transceiver that provides LVTTL-to-GTLP and  
GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or clock-enabled modes of  
data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a  
backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL)  
backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels,  
improved differential input, OEC™ circuitry, and TI-OPC™circuitry. Improved GTLP OEC and TI-OPC circuits  
minimize bus-settling time and have been designed and tested using several backplane models. The high drive  
allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 11 Ω.  
GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard  
JESD 8-3. The ac specification of the SN74GTLPH1612 is given only at the preferred higher noise margin GTLP,  
but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP  
(VTT = 1.5 V and VREF = 1 V) signal levels.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, UBT, TI-OPC, OEC, TI are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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