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74GTLPH1645DGVRE4

更新时间： 2024-09-08 21:54:11
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德州仪器 - TI 总线收发器
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17页 254K
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16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

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74GTLPH1645DGVRE4 数据手册

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SN74GTLPH1645  
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER  
www.ti.com  
SCES290D–OCTOBER 1999–REVISED JUNE 2005  
FEATURES  
DGG OR DGV PACKAGE  
•
•
•
•
Member of the Texas Instruments Widebus™  
Family  
(TOP VIEW)  
1DIR  
1A1  
1A2  
GND  
1A3  
1A4  
1OE  
1B1  
1
2
3
4
5
6
7
8
9
56  
55  
TI-OPC™ Circuitry Limits Ringing on  
Unevenly Loaded Backplanes  
54 1B2  
OEC™ Circuitry Improves Signal Integrity and  
Reduces Electromagnetic Interference  
GND  
1B3  
1B4  
53  
52  
51  
50  
Bidirectional Interface Between GTLP Signal  
Levels and LVTTL Logic Levels  
V
CC  
V
CC  
•
•
•
•
LVTTL Interfaces Are 5-V Tolerant  
High-Drive GTLP Outputs (100 mA)  
LVTTL Outputs (–24 mA/24 mA)  
GND  
1A5  
49 GND  
48 1B5  
47 1B6  
1A6 10  
GND  
1A7  
1A8  
GND  
1B7  
1B8  
11  
12  
13  
46  
45  
44  
Variable Edge-Rate Control (ERC) Input  
Selects GTLP Rise and Fall Times for Optimal  
Data-Transfer Rate and Signal Integrity in  
Distributed Loads  
GND 14  
ERC 15  
2A1 16  
2A2 17  
43 BIAS V  
CC  
42  
V
REF  
•
Ioff, Power-Up 3-State, and BIAS VCC Support  
Live Insertion  
41 2B1  
40 2B2  
•
•
Bus Hold on A-Port Data Inputs  
GND  
GND  
18  
39  
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
2A3 19  
2A4 20  
GND 21  
38 2B3  
37 2B4  
36 GND  
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
V
CC  
22  
35  
V
CC  
2A5 23  
2A6 24  
GND 25  
2A7 26  
2A8 27  
2DIR 28  
34 2B5  
33 2B6  
32 GND  
31 2B7  
30 2B8  
29 2OE  
DESCRIPTION/ORDERING INFORMATION  
The SN74GTLPH1645 is a high-drive, 16-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL  
signal-level translation. It is partitioned as two 8-bit transceivers. The device provides a high-speed interface  
between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed  
(about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced  
output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™  
circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and  
tested using several backplane models. The high drive allows incident-wave switching in heavily loaded  
backplanes with equivalent load impedance down to 11 Ω.  
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.  
The ac specification of the SN74GTLPH1645 is given only at the preferred higher noise-margin GTLP, but the  
user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and  
VREF = 1 V) signal levels.  
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,  
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input  
reference voltage.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, TI-OPC, OEC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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