Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> ZL30119GGG

ZL30119GGG

更新时间： 2024-02-13 07:33:20

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		ATM集成电路 SONET集成电路 SDH集成电路电信集成电路电信电路异步传输模式
页数	文件大小	规格书
27页	289K
描述
Low Jitter Line Card Synchronizer

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

ZL30119GGG 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	FBGA,	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.79
Is Samacsys：	N	应用程序：	SONET;SDH
JESD-30 代码：	S-PBGA-B100	JESD-609代码：	e0
长度：	9 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	FBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, FINE PITCH
峰值回流温度（摄氏度）：	225	认证状态：	Not Qualified
座面最大高度：	1.72 mm	标称供电电压：	1.8 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	9 mm	Base Number Matches：	1

ZL30119GGG 数据手册

ZL30119

Data Sheet

I/O

Pin #

Name

Description

Type

J10

p1_clk0

Programmable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be

configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in

addition to 2 kHz. The default frequency for this output is 1.544 MHz (DS1).

K10

p1_clk1

Programmable Synthesizer1 - Output Clock 1 (LVCMOS). This is a

programmable clock output configurable as a multiple or division of the p1_clk0

frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this

output is 3.088 MHz (2x DS1).

H10

fb_clk

Feedback Clock (LVCMOS). This output is a buffered copy of the feedback

clock for DPLL1. The frequency of this output always equals the frequency of the

selected reference.

dpll2_ref

DPLL2 Selected Output Reference (LVCMOS). This is a buffered copy of the

output of the reference selector for DPLL2. Switching between input reference

clocks at this output is not hitless.

diff0_p

diff0_n

Differential Output Clock 0 (LVPECL). This output can be configured to provide

any one of the available SDH clocks. The default frequency for this clock output

is 155.52 MHz.

B10

A10

diff1_p

diff1_n

Differential Output Clock 1 (LVPECL). This output can be configured to provide

any one of the available SDH clocks. The default frequency for this clock output

is 622.08 MHz clock.

Control

rst_b

Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To

ensure proper operation, the device must be reset after power-up. Reset should

be asserted for a minimum of 300 ns.

dpll1_hs_en

I_u

DPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high at

this input enables hitless reference switching. A logic low disables hitless

reference switching and re-aligns DPLL1’s output phase to the phase of the

selected reference input. This feature can also be controlled through software

registers. This pin is internally pull up to Vdd.

C2 dpll1_mod_sel0

D2 dpll1_mod_sel1

I_u

DPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the levels

on these pins determine the default mode of operation for DPLL1 (Automatic,

Normal, Holdover or Freerun). After reset, the mode of operation can be

controlled directly with these pins, or by accessing the dpll1_modesel register

through the serial interface. This pin is internally pull up to Vdd.

diff0_en

diff1_en

I_u

Differential Output 0 Enable (LVCMOS, Schmitt Trigger). When set high, the

differential LVPECL output 0 driver is enabled. When set low, the differential

driver is tristated reducing power consumption. This pin is internally pull up to

Vdd.

I_u

Differential Output 1 Enable (LVCMOS, Schmitt Trigger). When set high, the

differential LVPECL output 1 driver is enabled. When set low, the differential

driver is tristated reducing power consumption.This pin is internally pull up to

Vdd.

Zarlink Semiconductor Inc.

1...4 5 678 9 10...27

下载PDF

与ZL30119GGG相关器件

型号	品牌	描述	获取价格	数据表
ZL30119GGG2	ZARLINK	Low Jitter Line Card Synchronizer	获取价格
ZL30120	ZARLINK	SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer	获取价格
ZL30120	MICROCHIP	The ZL30120 Multi-Rate Line Card Synchronizer is a highly integrated device that provides	获取价格
ZL30120GGG	ZARLINK	SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer	获取价格
ZL30120GGG2	ZARLINK	SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer	获取价格
ZL30121	ZARLINK	SONET/SDH Low Jitter System Synchronizer	获取价格

与ZL30119GGG相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

17
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

17
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

14
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

11

产品中心

服务支持

精选活动

关于我们

帮助中心

ZL30119GGG

ZL30119GGG 技术参数

ZL30119GGG 数据手册

与ZL30119GGG相关器件

与ZL30119GGG相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ZL30119GGG

ZL30119GGG 技术参数

ZL30119GGG 数据手册

与ZL30119GGG相关器件

与ZL30119GGG相关文章

您还可以找

您在本页遇到什么问题？