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ZL30121GGGV2 PDF预览

ZL30121GGGV2

更新时间： 2024-09-28 15:58:55
品牌 Logo 应用领域
加拿大卓联 - ZARLINK ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
31页 231K
描述
Support Circuit, 1-Func, PBGA100, 9 X 9 MM, 0.80 MM PITCH, CABGA-100

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ZL30121GGGV2 技术参数

生命周期：Transferred包装说明：FBGA,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.8应用程序：SONET;SDH
JESD-30 代码：S-PBGA-B100长度：9 mm
功能数量：1端子数量：100
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：FBGA
封装形状：SQUARE封装形式：GRID ARRAY
认证状态：Not Qualified座面最大高度：1.72 mm
标称供电电压：1.8 V表面贴装：YES
电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT温度等级：INDUSTRIAL
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM宽度：9 mm
Base Number Matches：1

ZL30121GGGV2 数据手册

 浏览型号ZL30121GGGV2的Datasheet PDF文件第2页浏览型号ZL30121GGGV2的Datasheet PDF文件第3页浏览型号ZL30121GGGV2的Datasheet PDF文件第4页浏览型号ZL30121GGGV2的Datasheet PDF文件第5页浏览型号ZL30121GGGV2的Datasheet PDF文件第6页浏览型号ZL30121GGGV2的Datasheet PDF文件第7页 
ZL30121  
SONET/SDH  
Low Jitter System Synchronizer  
Data Sheet  
June 2008  
Features  
Ordering Information  
•
•
•
Supports the requirements of Telcordia GR-253 and  
GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and  
the requirements of ITU-T G.781 SETS, G.813  
SEC, G.823, G.824 and G.825 clocks  
ZL30121GGGV2  
100 Pin CABGA  
Trays  
Trays  
ZL30121GGG2V2 100 Pin CABGA**  
**Pb Free Tin/Silver/Copper  
Internal APLL provides standard output clock  
frequencies up to 622.08 MHz with jitter < 3 ps  
RMS suitable for GR-253-CORE OC-12 and G.813  
STM-16 interfaces  
-40oC to +85oC  
•
•
•
•
•
•
Supports master/slave configuration for  
AdvancedTCATM  
Programmable output synthesizers generate clock  
frequencies from any multiple of 8 kHz up to  
77.76 MHz in addition to 2 kHz  
Configurable input to output delay and output to  
output phase alignment  
•
•
Provides two DPLLs which are independently  
configurable through a serial software interface  
Optional external feedback path provides dynamic  
input to output delay compensation  
DPLL1 provides all the features necessary for  
generating SONET/SDH compliant clocks including  
automatic hitless reference switching, automatic  
mode selection (locked, free-run, holdover),  
selectable loop bandwidth and pull-in range  
Provides 3 sync inputs for output frame pulse  
alignment  
Generates several styles of output frame pulses  
with selectable pulse width, polarity and frequency  
•
•
DPLL2 provides a comprehensive set of features  
necessary for generating derived output clocks and  
other general purpose clocks  
Flexible input reference monitoring automatically  
disqualifies references based on frequency and  
phase irregularities  
Provides 8 reference inputs which support clock  
frequencies with any multiples of 8 kHz up to  
77.76 MHz in addition to 2 kHz  
•
Supports IEEE 1149.1 JTAG Boundary Scan  
dpll2_ref  
dpll1_holdover diff0_en diff1_en  
trst_b tck tdi tms tdo  
dpll1_hs_en  
dpll1_lock  
p0_clk0  
p0_clk1  
p0_fp0  
p0_fp1  
osco  
osci  
Master  
Clock  
IEEE 1449.1  
JTAG  
P0  
DPLL2  
Synthesizer  
ref  
ref  
ref0  
ref1  
ref2  
ref3  
ref4  
ref5  
ref6  
ref7  
p1_clk0  
p1_clk1  
P1  
Synthesizer  
ref7:0  
diff0_p/n  
diff1_p/n  
sdh_clk0  
sdh_clk1  
sdh_fp0  
sdh_fp1  
SONET/SDH  
APLL  
DPLL1  
sync0  
sync1  
sync2  
sync2:0  
sync  
fb_clk  
Feedback  
Synthesizer  
fb_clk  
fb_fp  
ref_&_sync_status  
Reference  
Monitors  
ext_fb_fp  
ext_fb_clk  
Controller &  
State Machine  
int_b  
SPI Interface  
sdh_filter filter_ref0 filter_ref1  
sck  
si  
so cs_b  
rst_b slave_en dpll1_mod_sel1:0  
Figure 1 - Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2006-2008, Zarlink Semiconductor Inc. All Rights Reserved.  
 
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