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ZL30132GGG2 PDF预览

ZL30132GGG2

更新时间: 2024-11-02 20:57:23
品牌 Logo 应用领域
加拿大卓联 - ZARLINK ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
9页 94K
描述
Support Circuit, 1-Func, PBGA64, 9 X 9 MM, 1 MM PITCH, LEAD FREE, CABGA-64

ZL30132GGG2 技术参数

生命周期:Transferred包装说明:BGA,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.8应用程序:SONET;SDH
JESD-30 代码:S-PBGA-B64JESD-609代码:e1
长度:9 mm功能数量:1
端子数量:64最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
座面最大高度:1.72 mm标称供电电压:1.8 V
表面贴装:YES电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT
温度等级:INDUSTRIAL端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:9 mm
Base Number Matches:1

ZL30132GGG2 数据手册

 浏览型号ZL30132GGG2的Datasheet PDF文件第2页浏览型号ZL30132GGG2的Datasheet PDF文件第3页浏览型号ZL30132GGG2的Datasheet PDF文件第4页浏览型号ZL30132GGG2的Datasheet PDF文件第5页浏览型号ZL30132GGG2的Datasheet PDF文件第6页浏览型号ZL30132GGG2的Datasheet PDF文件第7页 
ZL30132  
OC-192/STM-64 SONET/SDH/10GbE  
Network Interface Synchronizer  
Short Form Data Sheet  
July 2009  
Features  
Ordering Information  
Synchronizes to standard telecom or Ethernet  
ZL30132GGG  
ZL30132GGG2  
64 Pin CABGA  
64 Pin CABGA*  
Trays  
Trays  
backplane clocks and provides jitter filtered output  
clocks for SONET/SDH, PDH and Ethernet network  
interface cards  
*Pb Free Tin/Silver/Copper  
-40oC to +85oC  
Supports the requirements of ITU-T G.8262 for  
synchronous Ethernet Equipment slave Clocks  
(EEC option 1 and 2)  
Generates several styles of output frame pulses  
with selectable pulse width, polarity, and frequency  
Synchronizes to telecom reference clocks (2 kHz,  
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to  
Ethernet reference clocks (25 MHz, 50 MHz,  
62.5 MHz, 125 MHz)  
Configurable input to output delay and output to  
output phase alignment  
Configurable through a serial interface (SPI or I2C)  
Supports automatic hitless reference switching and  
short term holdover during loss of reference inputs  
DPLL can be configured to provide synchronous or  
asynchronous clock outputs  
Generates standard SONET/SDH clock rates (e.g.  
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,  
622.08 MHz) or Ethernet clock rates (e.g. 25 MHz,  
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for  
synchronizing Ethernet PHYs  
Supports IEEE 1149.1 JTAG Boundary Scan  
Applications  
ITU-T G.8262 Line Cards which support 1GbE and  
10GbE interfaces  
Programmable synthesizer generates clock  
frequencies with any multiple of 8 kHz up to  
100 MHz  
SONET line cards up to OC-192  
SDH line cards up to STM-64  
Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz,  
or 0.1 Hz  
osci  
osco  
/N1  
ref0  
ref1  
ref2  
SONET/  
Ethernet  
APLL  
diff  
/N2  
ref  
apll_clk  
DPLL  
Programmable  
Synthesizer  
N*8kHz  
sync0  
sync1  
sync2  
p_clk  
p_fp  
sync  
hold  
mode  
lock  
I2C/SPI  
JTAG  
Figure 1 - Simplified Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2008-2009, Zarlink Semiconductor Inc. All Rights Reserved.  

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