Datasheet > ZL30123

ZL30123

更新时间： 2023-12-06 20:09:45

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
27页	350K
描述
The ZL30123 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing an

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ZL30123 数据手册

ZL30123

SONET/SDH

Low Jitter Line Card Synchronizer

Data Sheet

May 2006

Features

Ordering Information

•

Synchronizes with standard telecom system

ZL30123GGG

100 Pin CABGA

Trays

references and synthesizes a wide variety of

protected telecom line interface clocks that are

compliant with Telcordia GR-253-CORE and ITU-T

G.813

ZL30123GGG2 100 Pin CABGA*

*Pb Free Tin/Silver/Copper

-40^oC to +85^oC

•

Internal APLL provides standard output clock

frequencies up to 622.08 MHz with jitter < 3 ps

RMS suitable for GR-253-CORE OC-12 and G.813

STM-16 interfaces

•

Provides 8 reference inputs which support clock

frequencies with any multiples of 8 kHz up to

77.76 MHz in addition to 2 kHz

Programmable output synthesizers (P0, P1)

generate clock frequencies from any multiple of

8 kHz up to 77.76 MHz in addition to 2 kHz

•

Provides 3 sync inputs for output frame pulse

alignment

Generates several styles of output frame pulses

with selectable pulse width, polarity, and frequency

•

Provides two DPLLs which are independently

configurable through a serial peripheral interface

Configurable input to output delay, and output to

output phase alignment

DPLL1 provides all the features necessary for

generating SONET/SDH compliant clocks including

automatic hitless reference switching, automatic

mode selection (locked, free-run, holdover), and

selectable loop bandwidth

Flexible input reference monitoring automatically

disqualifies references based on frequency and

phase irregularities

•

DPLL2 provides a comprehensive set of features

for generating derived output clocks and other

general purpose clocks

•

Supports IEEE 1149.1 JTAG Boundary Scan

dpll2_ref

dpll1_holdover diff0_en diff1_en

trst_b tck tdi tms tdo

dpll1_hs_en

dpll1_lock

p0_clk0

p0_clk1

p0_fp0

p0_fp1

osco

osci

Master

Clock

IEEE 1449.1

JTAG

DPLL2

Synthesizer

ref

ref0

ref1

ref2

ref3

ref4

ref5

ref6

ref7

p1_clk0

p1_clk1

Synthesizer

ref7:0

diff0

diff1

sdh_clk0

sdh_clk1

sdh_fp0

sdh_fp1

SONET/SDH

APLL

DPLL1

sync0

sync1

sync2

sync2:0

sync

fb_clk

Feedback

Synthesizer

fb_clk/fp

ref_&_sync_status

Reference

Monitors

Controller &

State Machine

int_b

SPI Interface

sdh_filter filter_ref0 filter_ref1

sck

so cs_b

rst_b

dpll1_mod_sel1:0

Figure 1 - Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...27

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与ZL30123相关器件

型号	品牌	获取价格	描述	数据表
ZL30123GGG	ZARLINK	获取价格	Low Jitter Line Card Synchronizer
ZL30123GGG2	ZARLINK	获取价格	Low Jitter Line Card Synchronizer
ZL30130	MICROCHIP	获取价格	The ZL30130 SONET/SDH/GbE Stratum 2/3E/3 System Synchronizer and SETS device is a highly i
ZL30131	ZARLINK	获取价格	OC-192/STM-64 SONET/SDH/10GbE Network Interface Synchronizer
ZL30131	MICROCHIP	获取价格	The ZL30131 OC-192/STM-64 PDH/SONET/SDH/10GbE Network Interface Synchronizer is a highly i
ZL30131GGG	ZARLINK	获取价格	OC-192/STM-64 SONET/SDH/10GbE Network Interface Synchronizer
ZL30131GGG2	ZARLINK	获取价格	OC-192/STM-64 SONET/SDH/10GbE Network Interface Synchronizer
ZL30132	MICROCHIP	获取价格	The ZL30132 OC-192/STM-64 SONET/SDH/10GbE Network Interface Synchronizer is a highly integ
ZL30132GGG	MICROSEMI	获取价格	Support Circuit, 1-Func, PBGA64, 9 X 9 MM, 1 MM PITCH, CABGA-64
ZL30132GGG2	ZARLINK	获取价格	Support Circuit, 1-Func, PBGA64, 9 X 9 MM, 1 MM PITCH, LEAD FREE, CABGA-64

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