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ZL30121

更新时间： 2024-09-29 14:55:59
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美国微芯 - MICROCHIP /
页数 文件大小 规格书
31页 376K
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The ZL30121 SONET/SDH System Synchronizer is a highly integrated device that provides the function

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ZL30121 数据手册

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ZL30121  
SONET/SDH  
Low Jitter System Synchronizer  
Data Sheet  
June 2008  
Features  
Ordering Information  
•
•
•
Supports the requirements of Telcordia GR-253 and  
GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and  
the requirements of ITU-T G.781 SETS, G.813  
SEC, G.823, G.824 and G.825 clocks  
ZL30121GGGV2  
100 Pin CABGA  
Trays  
Trays  
ZL30121GGG2V2 100 Pin CABGA**  
**Pb Free Tin/Silver/Copper  
Internal APLL provides standard output clock  
frequencies up to 622.08 MHz with jitter < 3 ps  
RMS suitable for GR-253-CORE OC-12 and G.813  
STM-16 interfaces  
-40oC to +85oC  
•
•
•
•
•
•
Supports master/slave configuration for  
AdvancedTCATM  
Programmable output synthesizers generate clock  
frequencies from any multiple of 8 kHz up to  
77.76 MHz in addition to 2 kHz  
Configurable input to output delay and output to  
output phase alignment  
•
•
Provides two DPLLs which are independently  
configurable through a serial software interface  
Optional external feedback path provides dynamic  
input to output delay compensation  
DPLL1 provides all the features necessary for  
generating SONET/SDH compliant clocks including  
automatic hitless reference switching, automatic  
mode selection (locked, free-run, holdover),  
selectable loop bandwidth and pull-in range  
Provides 3 sync inputs for output frame pulse  
alignment  
Generates several styles of output frame pulses  
with selectable pulse width, polarity and frequency  
•
•
DPLL2 provides a comprehensive set of features  
necessary for generating derived output clocks and  
other general purpose clocks  
Flexible input reference monitoring automatically  
disqualifies references based on frequency and  
phase irregularities  
Provides 8 reference inputs which support clock  
frequencies with any multiples of 8 kHz up to  
77.76 MHz in addition to 2 kHz  
•
Supports IEEE 1149.1 JTAG Boundary Scan  
dpll2_ref  
dpll1_holdover diff0_en diff1_en  
trst_b tck tdi tms tdo  
dpll1_hs_en  
dpll1_lock  
p0_clk0  
p0_clk1  
p0_fp0  
p0_fp1  
osco  
osci  
Master  
Clock  
IEEE 1449.1  
JTAG  
P0  
DPLL2  
Synthesizer  
ref  
ref  
ref0  
ref1  
ref2  
ref3  
ref4  
ref5  
ref6  
ref7  
p1_clk0  
p1_clk1  
P1  
Synthesizer  
ref7:0  
diff0_p/n  
diff1_p/n  
sdh_clk0  
sdh_clk1  
sdh_fp0  
sdh_fp1  
SONET/SDH  
APLL  
DPLL1  
sync0  
sync1  
sync2  
sync2:0  
sync  
fb_clk  
Feedback  
Synthesizer  
fb_clk  
fb_fp  
ref_&_sync_status  
Reference  
Monitors  
ext_fb_fp  
ext_fb_clk  
Controller &  
State Machine  
int_b  
SPI Interface  
sdh_filter filter_ref0 filter_ref1  
sck  
si  
so cs_b  
rst_b slave_en dpll1_mod_sel1:0  
Figure 1 - Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2006-2008, Zarlink Semiconductor Inc. All Rights Reserved.  
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