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ZL30131 PDF预览

ZL30131

更新时间: 2023-12-06 20:08:37
品牌 Logo 应用领域
美国微芯 - MICROCHIP 光电二极管
页数 文件大小 规格书
125页 1086K
描述
The ZL30131 OC-192/STM-64 PDH/SONET/SDH/10GbE Network Interface Synchronizer is a highly integrate

ZL30131 数据手册

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ZL30131  
OC-192/STM-64 SONET/SDH/10GbE  
Network Interface Synchronizer  
Data Sheet  
July 2009  
Features  
Ordering Information  
Synchronizes to standard telecom or Ethernet  
backplane clocks and provides jitter filtered output  
clocks for SONET/SDH, PDH and Ethernet network  
interface cards  
ZL30131GGG  
ZL30131GGG2 100 Pin CABGA*  
100 Pin CABGA  
Trays  
Trays  
*Pb Free Tin/Silver/Copper  
-40oC to +85oC  
Supports the requirements of ITU-T G.8262 for  
synchronous Ethernet Equipment slave Clocks  
(EEC option 1 and 2)  
Programmable output synthesizers (P0, P1)  
generate telecom clock frequencies from any  
multiple of 8 kHz up to 100 MHz (e.g., T1/E1,  
DS3/E3)  
Two independent DPLLs provides timing for the  
transmit path (backplane to line rate) and the  
receive path (recovered line rate to backplane)  
Synchronizes to telecom reference clocks (2 kHz,  
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to  
Ethernet reference clocks (25 MHz, 50 MHz,  
62.5 MHz, 125 MHz)  
Generates several styles of output frame pulses  
with selectable pulse width, polarity, and frequency  
Configurable input to output delay and output to  
output phase alignment  
Configurable through a serial interface (SPI or I2C)  
Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz,  
or 0.1 Hz  
Supports automatic hitless reference switching and  
short term holdover during loss of reference inputs  
DPLLs can be configured to provide synchronous  
or asynchronous clock outputs  
Generates standard SONET/SDH clock rates (e.g.,  
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,  
622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,  
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for  
synchronizing Ethernet PHYs  
Applications  
ITU-T G.8262 Line Cards which support 1 GbE  
and 10 GbE interfaces  
SONET line cards up to OC-192  
SDH line cards up to STM-64  
ref_out  
osci  
osco  
ref0  
/N1  
/N2  
diff0_p/n  
diff1_p/n  
ref1  
ref2  
ref3  
ref4  
ref5  
ref6  
ref7  
Tx  
DPLL  
APLL  
P0  
apll_clk0  
apll_clk1  
Input  
Ports  
p0_clk0  
p0_clk1  
p0_fp0  
p0_fp1  
sync0  
sync1  
sync2  
Ref Mon  
Tx  
ref0  
ref7  
p1_clk0  
p1_clk1  
P1  
Rx  
DPLL  
Rx  
lock  
I2C/SPI  
mode hold  
JTAG  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2008-2009, Zarlink Semiconductor Inc. All Rights Reserved.  

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