ZL30121
SONET/SDH
Low Jitter System Synchronizer
Data Sheet
May 2006
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Ordering Information
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ZL30121GGG
100 Pin CABGA
Trays
Trays
ZL30121GGG2 100 Pin CABGA*
Features
*Pb Free Tin/Silver/Copper
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Supports the requirements of Telcordia GR-253 and
GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and
the requirements of ITU-T G.781 SETS, G.813
SEC, G.823, G.824 and G.825 clocks
Internal APLL provides standard output clock
frequencies up to 622.08 MHz with jitter < 3 ps
RMS suitable for GR-253-CORE OC-12 and G.813
STM-16 interfaces
-40oC to +85oC
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Provides 8 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
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Supports master/slave configuration for
AdvancedTCATM
Programmable output synthesizers generate clock
frequencies from any multiple of 8 kHz up to
77.76 MHz in addition to 2 kHz
Configurable input to output delay and output to
output phase alignment
Optional external feedback path provides dynamic
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Provides two DPLLs which are independently
input to output delay compensation
configurable through a serial software interface
Provides 3 sync inputs for output frame pulse
alignment
DPLL1 provides all the features necessary for
generating SONET/SDH compliant clocks including
automatic hitless reference switching, automatic
mode selection (locked, free-run, holdover),
selectable loop bandwidth and pull-in range
Generates several styles of output frame pulses
with selectable pulse width, polarity and frequency
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
Supports IEEE 1149.1 JTAG Boundary Scan
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DPLL2 provides a comprehensive set of features
necessary for generating derived output clocks and
other general purpose clocks
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dpll2_ref
dpll1_holdover diff0_en diff1_en
trst_b tck tdi tms tdo
dpll1_hs_en
dpll1_lock
p0_clk0
p0_clk1
p0_fp0
p0_fp1
p1_clk0
p1_clk1
osco
osci
Master
Clock
IEEE 1449.1
JTAG
P0
DPLL2
Synthesizer
ref
ref
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
P1
Synthesizer
ref7:0
diff0_p/n
diff1_p/n
sdh_clk0
sdh_clk1
sdh_fp0
sdh_fp1
SONET/SDH
APLL
DPLL1
sync0
sync1
sync2
sync2:0
sync
fb_clk
Feedback
fb_clk
fb_fp
ref_&_sync_status
Reference
Monitors
Synthesizer
ext_fb_fp
ext_fb_clk
Controller &
int_b
SPI Interface
State Machine
sdh_filter filter_ref0 filter_ref1
sck
si
so cs_b
rst_b slave_en dpll1_mod_sel1:0
Figure 1 - Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.