Datasheet > ZL30120

ZL30120

更新时间： 2024-02-06 01:02:30

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		以太网
页数	文件大小	规格书
27页	324K
描述
SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer

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中文翻译

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数据手册

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ZL30120 数据手册

ZL30120

SONET/SDH/Ethernet

Multi-Rate Line Card Synchronizer

Data Sheet

May 2006

A full Design Manual is available to qualified customers.

Ordering Information

please

send

ZL30120GGG

100 Pin CABGA

Trays

TimingandSync@Zarlink.com.

ZL30120GGG2 100 Pin CABGA** Trays

**Pb Free Tin/Silver/Copper

Features

-40^oC to +85^oC

•

Synchronizes with standard telecom system

references and synthesizes a wide variety of

protected telecom line interface clocks that are

•

Provides two DPLLs which have independent

modes of operation (locked, free-run, holdover)

and optional hitless reference switching.

Flexible input reference monitoring automatically

disqualifies references based on frequency and

phase irregularities

compliant with Telcordia GR-1244-CORE, GR-253-

CORE, ITU-T G.813, and compatible with ITU-T

G.8261 (formerly G.pactiming)

•

Internal low jitter APLL provides SONET/SDH

clocks including 6.48 MHz, 19.44 MHz, 38.88 MHz,

51.84 MHz and 77.76 MHz, or 25 MHz and 50 MHz

Synchronous Ethernet output clocks

•

Provides 3 sync inputs for output frame pulse

alignment

•

Programmable output synthesizers (P0, P1)

generate general purpose clock frequencies from

any multiple of 8 kHz up to 100 MHz

Jitter performance of <8 ps RMS on the low jitter

APLL outputs, and <20 ps RMS on the

programmable synthesizer outputs.

Provides 8 reference inputs which support clock

frequencies with any multiples of 8 kHz up to

77.76 MHz in addition to 2 kHz

Generates several styles of output frame pulses

with selectable pulse width, polarity, and frequency

Configurable input to output delay, and output to

output phase alignment

Supports IEEE 1149.1 JTAG Boundary Scan

dpll2_ref

dpll1_holdover

trst_b tck tdi tms tdo

dpll1_hs_en

dpll1_lock

p0_clk0

p0_clk1

p0_fp0

p0_fp1

p1_clk0

p1_clk1

osco

osci

Master

Clock

IEEE 1449.1

JTAG

DPLL2

Synthesizer

ref

ref0

ref1

ref2

ref3

ref4

ref5

ref6

ref7

Synthesizer

ref7:0

apll_clk0

apll_clk1

apll_fp0

apll_fp1

Low Jitter

APLL

DPLL1

sync0

sync1

sync2

sync2:0

sync

fb_clk

Feedback

fb_clk/fp

ref_&_sync_status

Reference

Monitors

Synthesizer

Controller &

int_b

SPI Interface

State Machine

apll_filter filter_ref0 filter_ref1

sck

so cs_b

rst_b

dpll1_mod_sel1:0

Figure 1 - Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...27

中文翻译

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与ZL30120相关器件

型号	品牌	获取价格	描述	数据表
ZL30120GGG	ZARLINK	获取价格	SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
ZL30120GGG2	ZARLINK	获取价格	SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
ZL30121	ZARLINK	获取价格	SONET/SDH Low Jitter System Synchronizer
ZL30121	MICROCHIP	获取价格	The ZL30121 SONET/SDH System Synchronizer is a highly integrated device that provides the
ZL30121GGG	ZARLINK	获取价格	SONET/SDH Low Jitter System Synchronizer
ZL30121GGG2	ZARLINK	获取价格	SONET/SDH Low Jitter System Synchronizer
ZL30121GGGV2	ZARLINK	获取价格	Support Circuit, 1-Func, PBGA100, 9 X 9 MM, 0.80 MM PITCH, CABGA-100
ZL30122	ZARLINK	获取价格	SONET/SDH Low Jitter Line Card Synchronizer
ZL30122	MICROCHIP	获取价格	The ZL30122 SONET/SDH Line Card Synchronizer is a highly integrated device that provides t
ZL30122GGG	ZARLINK	获取价格	SONET/SDH Low Jitter Line Card Synchronizer

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