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ZL30122GGG PDF预览

ZL30122GGG

更新时间： 2024-02-12 15:49:39
品牌 Logo 应用领域
加拿大卓联 - ZARLINK ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
23页 260K
描述
SONET/SDH Low Jitter Line Card Synchronizer

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ZL30122GGG 技术参数

生命周期：Transferred包装说明：BGA,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.8Is Samacsys：N
应用程序：SONET;SDHJESD-30 代码：S-PBGA-B64
JESD-609代码：e0长度：9 mm
功能数量：1端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：SQUARE封装形式：GRID ARRAY
认证状态：Not Qualified座面最大高度：1.72 mm
标称供电电压：1.8 V表面贴装：YES
电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
宽度：9 mmBase Number Matches：1

ZL30122GGG 数据手册

 浏览型号ZL30122GGG的Datasheet PDF文件第2页浏览型号ZL30122GGG的Datasheet PDF文件第3页浏览型号ZL30122GGG的Datasheet PDF文件第4页浏览型号ZL30122GGG的Datasheet PDF文件第5页浏览型号ZL30122GGG的Datasheet PDF文件第6页浏览型号ZL30122GGG的Datasheet PDF文件第7页 
ZL30122  
SONET/SDH  
Low Jitter Line Card Synchronizer  
Data Sheet  
May 2006  
A full Design Manual is available to qualified customers.  
Ordering Information  
To  
register,  
please  
send  
an  
email  
to  
ZL30122GGG  
64 Pin CABGA  
Trays  
Trays  
TimingandSync@Zarlink.com.  
ZL30122GGG2 64 Pin CABGA*  
*Pb Free Tin/Silver/Copper  
Features  
-40oC to +85oC  
•
Synchronizes with standard telecom system  
references and synthesizes a wide variety of  
protected telecom line interface clocks that are  
•
Provides 3 reference inputs which support clock  
frequencies with any multiples of 8 kHz up to  
77.76 MHz in addition to 2 kHz  
compliant with Telcordia GR-253-CORE and ITU-T  
G.813  
•
Internal APLL provides standard output clock  
frequencies up to 622.08 MHz with jitter < 3 ps  
RMS suitable for GR-253-CORE OC-12 and G.813  
STM-16 interfaces  
•
•
•
•
Provides 3 sync inputs for output frame pulse  
alignment  
Generates several styles of output frame pulses  
with selectable pulse width, polarity, and frequency  
•
•
Programmable output synthesizer generates clock  
frequencies from any multiple of 8 kHz up to  
77.76 MHz in addition to 2 kHz  
Configurable input to output delay, and output to  
output phase alignment  
Flexible input reference monitoring automatically  
disqualifies references based on frequency and  
phase irregularities  
Digital Phase Locked-Loop (DPLL) provides all the  
features necessary for generating SONET/SDH  
compliant clocks including automatic hitless  
reference switching, automatic mode selection  
(locked, free-run, holdover), and selectable loop  
bandwidth  
•
Supports IEEE 1149.1 JTAG Boundary Scan  
dpll_holdover  
dpll_lock  
diff_en  
trst_b tck tdi tms tdo  
osco  
osci  
Master  
Clock  
IEEE 1449.1  
JTAG  
ref0  
ref1  
ref2  
ref2:0  
ref  
diff_clk_p/n  
SONET/SDH  
sdh_clk  
sdh_fp  
APLL  
DPLL  
p_clk  
p_fp  
Programmable  
Synthesizer  
sync0  
sync1  
sync2  
sync2:0  
sync  
ref_&_sync_status  
Reference  
Monitors  
Controller &  
int_b  
SPI Interface  
State Machine  
sdh_filter filter_ref0 filter_ref1  
sck  
si  
so cs_b  
rst_b  
dpll_mod_sel  
Figure 1 - Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.  
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