Datasheet > ZL30131GGG

ZL30131GGG

更新时间： 2024-01-17 12:49:23

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		网络接口以太网
页数	文件大小	规格书
11页	232K
描述
OC-192/STM-64 SONET/SDH/10GbE Network Interface Synchronizer

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中文翻译

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技术参数
数据手册

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ZL30131GGG 技术参数

生命周期：	Transferred	包装说明：	FBGA,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.8	应用程序：	SONET;SDH
JESD-30 代码：	S-PBGA-B100	长度：	9 mm
功能数量：	1	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	FBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, FINE PITCH
认证状态：	Not Qualified	座面最大高度：	1.72 mm
标称供电电压：	1.8 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	宽度：	9 mm
Base Number Matches：	1

ZL30131GGG 数据手册

ZL30131

OC-192/STM-64 SONET/SDH/10GbE

Network Interface Synchronizer

Short Form Data Sheet

February 2008

Features

Ordering Information

•

Synchronizes to standard telecom or Ethernet

backplane clocks and provides jitter filtered output

clocks for SONET/SDH, PDH and Ethernet network

interface cards

ZL30131GGG

ZL30131GGG2 100 Pin CABGA*

100 Pin CABGA

Trays

*Pb Free Tin/Silver/Copper

•

Supports the requirements of ITU-T G.8262 for

synchronous Ethernet Equipment slave Clocks

(EEC option 1 and 2)

-40 C to +85 C

multiple of 8 kHz up to 100 MHz (e.g., T1/E1,

DS3/E3)

Two independent DPLLs provides timing for the

transmit path (backplane to line rate) and the

receive path (recovered line rate to backplane)

•

Generates several styles of output frame pulses

with selectable pulse width, polarity, and frequency

Synchronizes to telecom reference clocks (2 kHz,

N*8 kHz up to 77.76 MHz, 155.52 MHz) or to

Ethernet reference clocks (25 MHz, 50 MHz,

62.5 MHz, 125 MHz)

Configurable input to output delay and output to

output phase alignment

•

Configurable through a serial interface (SPI or I C)

•

Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz,

or 0.1 Hz

DPLLs can be configured to provide synchronous

or asynchronous clock outputs

Supports automatic hitless reference switching and

short term holdover during loss of reference inputs

Applications

Generates standard SONET/SDH clock rates (e.g.,

19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,

622.08 MHz) or Ethernet clock rates (e.g. 25 MHz,

50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for

synchronizing Ethernet PHYs

•

ITU-T G.8262 Line Cards which support 1GbE and

10GbE interfaces

•

SONET line cards up to OC-192

SDH line cards up to STM-64

•

Programmable output synthesizers (P0, P1)

generate telecom clock frequencies from any

ref_out

osci

osco

ref0

/N1

/N2

diff0_p/n

diff1_p/n

ref1

ref2

ref3

ref4

ref5

ref6

ref7

DPLL

APLL

apll_clk0

apll_clk1

Input

Ports

p0_clk0

p0_clk1

p0_fp0

p0_fp1

sync0

sync1

sync2

Ref Mon

ref0

ref7

p1_clk0

p1_clk1

DPLL

lock

I²C/SPI

mode hold

JTAG

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...11

中文翻译

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与ZL30131GGG相关器件

型号	品牌	获取价格	描述	数据表
ZL30131GGG2	ZARLINK	获取价格	OC-192/STM-64 SONET/SDH/10GbE Network Interface Synchronizer
ZL30132	MICROCHIP	获取价格	The ZL30132 OC-192/STM-64 SONET/SDH/10GbE Network Interface Synchronizer is a highly integ
ZL30132GGG	MICROSEMI	获取价格	Support Circuit, 1-Func, PBGA64, 9 X 9 MM, 1 MM PITCH, CABGA-64
ZL30132GGG2	ZARLINK	获取价格	Support Circuit, 1-Func, PBGA64, 9 X 9 MM, 1 MM PITCH, LEAD FREE, CABGA-64
ZL30132GGG2	MICROSEMI	获取价格	Support Circuit, 1-Func, PBGA64, 9 X 9 MM, 1 MM PITCH, LEAD FREE, CABGA-64
ZL30136	MICROCHIP	获取价格	The ZL30136 GbE and Telecom Rate Network Interface Synchronizer is a highly integrated cos
ZL30136GG2	MICROSEMI	获取价格	Ethernet Transceiver, PBGA64, 9 X 9 MM, 1 MM PITCH, LEAD FREE, CABGA-64
ZL30136GGG	MICROSEMI	获取价格	Ethernet Transceiver, PBGA64, CABGA-64
ZL30136GGG2	MICROSEMI	获取价格	Telecom IC, PBGA64,
ZL30138	MICROCHIP	获取价格	The ZL30138 SONET/SDH/Ethernet Stratum 2/3E/3 System Synchronizer and SETS device is a hig

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