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ZL30123GGG

更新时间： 2024-11-21 02:59:23
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
27页 328K
描述
Low Jitter Line Card Synchronizer

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中文翻译

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ZL30123GGG 技术参数

生命周期：Transferred包装说明：FBGA,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.8应用程序：SONET;SDH
JESD-30 代码：S-PBGA-B100JESD-609代码：e0
长度：9 mm功能数量：1
端子数量：100最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：FBGA封装形状：SQUARE
封装形式：GRID ARRAY, FINE PITCH认证状态：Not Qualified
座面最大高度：1.72 mm标称供电电压：1.8 V
表面贴装：YES电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM宽度：9 mm
Base Number Matches：1

ZL30123GGG 数据手册

 浏览型号ZL30123GGG的Datasheet PDF文件第2页浏览型号ZL30123GGG的Datasheet PDF文件第3页浏览型号ZL30123GGG的Datasheet PDF文件第4页浏览型号ZL30123GGG的Datasheet PDF文件第5页浏览型号ZL30123GGG的Datasheet PDF文件第6页浏览型号ZL30123GGG的Datasheet PDF文件第7页 
ZL30123  
SONET/SDH  
Low Jitter Line Card Synchronizer  
Data Sheet  
May 2006  
A full Design Manual is available to qualified customers.  
Ordering Information  
To  
register,  
please  
send  
an  
email  
to  
ZL30123GGG  
100 Pin CABGA  
Trays  
Trays  
TimingandSync@Zarlink.com.  
ZL30123GGG2 100 Pin CABGA*  
*Pb Free Tin/Silver/Copper  
Features  
-40oC to +85oC  
•
Synchronizes with standard telecom system  
references and synthesizes a wide variety of  
protected telecom line interface clocks that are  
•
•
DPLL2 provides a comprehensive set of features  
for generating derived output clocks and other  
general purpose clocks  
Provides 8 reference inputs which support clock  
frequencies with any multiples of 8 kHz up to  
77.76 MHz in addition to 2 kHz  
compliant with Telcordia GR-253-CORE and ITU-T  
G.813  
•
•
Internal APLL provides standard output clock  
frequencies up to 622.08 MHz with jitter < 3 ps  
RMS suitable for GR-253-CORE OC-12 and G.813  
STM-16 interfaces  
Programmable output synthesizers (P0, P1)  
generate clock frequencies from any multiple of  
8 kHz up to 77.76 MHz in addition to 2 kHz  
•
•
•
•
Provides 3 sync inputs for output frame pulse  
alignment  
Generates several styles of output frame pulses  
with selectable pulse width, polarity, and frequency  
•
•
Provides two DPLLs which are independently  
Configurable input to output delay, and output to  
configurable through a serial peripheral interface  
output phase alignment  
DPLL1 provides all the features necessary for  
generating SONET/SDH compliant clocks including  
automatic hitless reference switching, automatic  
mode selection (locked, free-run, holdover), and  
selectable loop bandwidth  
Flexible input reference monitoring automatically  
disqualifies references based on frequency and  
phase irregularities  
Supports IEEE 1149.1 JTAG Boundary Scan  
•
dpll2_ref  
dpll1_holdover diff0_en diff1_en  
trst_b tck tdi tms tdo  
dpll1_hs_en  
dpll1_lock  
p0_clk0  
p0_clk1  
p0_fp0  
p0_fp1  
p1_clk0  
p1_clk1  
osco  
osci  
Master  
Clock  
IEEE 1449.1  
JTAG  
P0  
DPLL2  
Synthesizer  
ref  
ref  
ref0  
ref1  
ref2  
ref3  
ref4  
ref5  
ref6  
ref7  
P1  
Synthesizer  
ref7:0  
diff0  
diff1  
sdh_clk0  
sdh_clk1  
sdh_fp0  
sdh_fp1  
SONET/SDH  
APLL  
DPLL1  
sync0  
sync1  
sync2  
sync2:0  
sync  
fb_clk  
Feedback  
fb_clk/fp  
ref_&_sync_status  
Reference  
Monitors  
Synthesizer  
Controller &  
int_b  
SPI Interface  
State Machine  
sdh_filter filter_ref0 filter_ref1  
sck  
si  
so cs_b  
rst_b  
dpll1_mod_sel1:0  
Figure 1 - Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.  
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