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UPA2711GR-E2 PDF预览

UPA2711GR-E2

更新时间: 2024-09-13 21:15:47
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
7页 149K
描述
TRANSISTOR,MOSFET,P-CHANNEL,30V V(BR)DSS,13A I(D),SO

UPA2711GR-E2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:,Reach Compliance Code:unknown
风险等级:5.92配置:Single
最大漏极电流 (Abs) (ID):13 AFET 技术:METAL-OXIDE SEMICONDUCTOR
工作模式:ENHANCEMENT MODE最高工作温度:150 °C
极性/信道类型:P-CHANNEL最大功率耗散 (Abs):2 W
子类别:Other Transistors表面贴装:YES
Base Number Matches:1

UPA2711GR-E2 数据手册

 浏览型号UPA2711GR-E2的Datasheet PDF文件第2页浏览型号UPA2711GR-E2的Datasheet PDF文件第3页浏览型号UPA2711GR-E2的Datasheet PDF文件第4页浏览型号UPA2711GR-E2的Datasheet PDF文件第5页浏览型号UPA2711GR-E2的Datasheet PDF文件第6页浏览型号UPA2711GR-E2的Datasheet PDF文件第7页 
DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
µ PA2711GR  
SWITCHING  
P-CHANNEL POWER MOS FET  
PACKAGE DRAWING (Unit: mm)  
DESCRIPTION  
The µ PA2711GR is P-Channel MOS Field Effect Transistor  
designed for power management applications of notebook  
computers and Li-ion battery protection circuit.  
8
5
1, 2, 3  
4
: Source  
: Gate  
5, 6, 7, 8 : Drain  
FEATURES  
Low on-state resistance  
RDS(on)1 = 9 mMAX. (VGS = 10 V, ID = 6.5 A)  
RDS(on)2 = 15 mMAX. (VGS = 4.5 V, ID = 6.5 A)  
6.0 ±0.3  
4.4  
1
4
5.37 MAX.  
0.8  
RDS(on)3 = 20 mMAX. (VGS = 4.0 V, ID = 6.5 A)  
Low Ciss: Ciss = 2450 pF TYP.  
Small and surface mount package (Power SOP8)  
0.5 ±0.2  
0.10  
1.27 0.78 MAX.  
ORDERING INFORMATION  
+0.10  
0.40  
0.12 M  
–0.05  
PART NUMBER  
PACKAGE  
µ PA2711GR  
Power SOP8  
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, Unless otherwise noted, All terminals are connected.)  
Drain to Source Voltage (VGS = 0 V)  
Gate to Source Voltage (VDS = 0 V)  
Drain Current (DC)  
VDSS  
VGSS  
ID(DC)  
ID(pulse)  
PT1  
PT2  
Tch  
Tstg  
IAS  
–30  
m20  
m13  
m52  
2
2
150  
V
V
A
EQUIVALENT CIRCUIT  
Drain Current (pulse) Note1  
A
Drain  
Note2  
Total Power Dissipation  
Total Power Dissipation  
W
W
°C  
°C  
A
Note3  
Body  
Diode  
Gate  
Channel Temperature  
Storage Temperature  
–55 to + 150  
13  
Single Avalanche Current Note4  
Single Avalanche Energy Note4  
Source  
EAS  
16.9  
mJ  
Notes 1. PW 10 µs, Duty Cycle 1%  
2. Mounted on ceramic substrate of 1200 mm2 x 2.2 mm  
3. Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec  
4. Starting Tch = 25°C, VDD = –15 V, RG = 25 , L = 100 µH, VGS = –20 0 V  
Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately  
degrade the device operation. Steps must be taken to stop generation of static electricity as much as  
possible, and quickly dissipate it once, when it has occurred.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. G15979EJ1V0DS00 (1st edition)  
Date Published March 2004 NS CP(K)  
Printed in Japan  
2004  

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