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UPA1917TE PDF预览

UPA1917TE

更新时间: 2024-11-22 22:41:43
品牌 Logo 应用领域
日电电子 - NEC 晶体晶体管场效应晶体管开关
页数 文件大小 规格书
8页 75K
描述
P-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING

UPA1917TE 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:SC-95包装说明:SMALL OUTLINE, R-PDSO-G6
针数:6Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8541.21.00.95
风险等级:5.32配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:20 V最大漏极电流 (ID):6 A
最大漏源导通电阻:0.07 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JESD-30 代码:R-PDSO-G6JESD-609代码:e0
元件数量:1端子数量:6
工作模式:ENHANCEMENT MODE封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED极性/信道类型:P-CHANNEL
认证状态:Not Qualified表面贴装:YES
端子面层:TIN LEAD端子形式:GULL WING
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
晶体管应用:SWITCHING晶体管元件材料:SILICON

UPA1917TE 数据手册

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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
µPA1917  
P-CHANNEL MOS FIELD EFFECT TRANSISTOR  
FOR SWITCHING  
DESCRIPTION  
PACKAGE DRAWING (Unit : mm)  
The µPA1917 is a switching device which can be driven  
directly by a 1.8 V power source.  
+0.1  
–0.05  
+0.1  
–0.06  
0.32  
0.16  
This device features a low on-state resistance and excellent  
switching characteristics, and is suitable for applications such  
as power switch of portable machine and so on.  
6
1
5
2
4
3
0 to 0.1  
FEATURES  
1.8 V drive available  
Low on-state resistance  
RDS(on)1 = 53 mMAX. (VGS = –4.5 V, ID = –3.0 A)  
RDS(on)2 = 70 mMAX. (VGS = –2.5 V, ID = –3.0 A)  
RDS(on)3 = 107 mMAX. (VGS = –1.8 V, ID = –1.5 A)  
0.65  
0.95 0.95  
1.9  
0.9 to 1.1  
2.9 ±0.2  
ORDERING INFORMATION  
1, 2, 5, 6 : Drain  
3
4
: Gate  
: Source  
PART NUMBER  
PACKAGE  
µPA1917TE  
SC-95 (Mini Mold Thin Type)  
EQUIVALENT CIRCUIT  
Marking : TR  
Drain  
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)  
Drain to Source Voltage (VGS = 0 V)  
Gate to Source Voltage (VDS = 0 V)  
Drain Current (DC) (TA = 25°C)  
Drain Current (pulse) Note1  
Total Power Dissipation  
VDSS  
VGSS  
ID(DC)  
ID(pulse)  
PT1  
–20  
V
Body  
Diode  
Gate  
V
A
m8.0  
m6.0  
Gate  
Protection  
Diode  
A
m24  
0.2  
Source  
W
W
°C  
Total Power Dissipation Note2  
PT2  
2.0  
Channel Temperature  
Tch  
150  
Storage Temperature  
Tstg  
–55 to +150 °C  
Notes 1. PW 10 µs, Duty Cycle 1%  
2. Mounted on FR-4 board, t 5 sec.  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When  
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated  
voltage may be applied to this device.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No.  
Date Published June 2002 NS CP(K)  
Printed in Japan  
G15925EJ1V0DS00 (1st edition)  
©
2002  

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