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TNETA1575PGC

更新时间： 2024-11-06 12:21:59

品牌	Logo	应用领域
德州仪器 - TI		异步传输模式 PC ATM
页数	文件大小	规格书
45页	693K
描述
ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES

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技术参数
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TNETA1575PGC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	FQFP, QFP240,1.3SQ,20	针数：	240
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.82	应用程序：	ATM
JESD-30 代码：	S-PQFP-G240	长度：	32 mm
功能数量：	1	端子数量：	240
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装等效代码：	QFP240,1.3SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, FINE PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3,5 V	认证状态：	Not Qualified
座面最大高度：	4.2 mm	子类别：	ATM/SONET/SDH ICs
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	ATM/SONET/SDH SEGMENTATION AND REASSEMBLY DEVICE
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	32 mm
Base Number Matches：	1

TNETA1575PGC 数据手册

TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

Supports Segmentation and Reassembly of

Host Accesses to the PHY-Layer Device

Can Be Performed Indirectly via the

TNETA1575 Local Peripheral Bus

AAL5 Packets in Accordance With ITU-T

Specifications I.361 and I.363

(11/93 Update)

Local Peripheral Bus Maps the PHY Device

Into the TNETA1575 PCI-Bus Address

Space

Integrated 32-Bit PCI Bus 2.1 (06/95)

Interface for Transferring Packet Data to

and From Host Memory

Supports Easy Access to AAL5 Trailer

Information

Provides Simultaneous Segmentation of up

to 2048 Packets

Supports Buffer Scatter/Gather (Transmit

and Receive Buffer Chaining)

Provides Simultaneous Reassembly of up

to 2048 Packets

Optional Early Segmentation of Packets, So

Segmentation Begins Once a Transmit

Buffer Is Filled, Instead of Waiting for the

Entire Packet to Be Available in Host

Memory

Provides Full VPI/VCI Support (12 VPI Bits

and 16 VCI Bits) for Transmit and Receive

Operations

Supports Constant-Bit-Rate (CBR) Traffic

via High-Priority Mechanism or Local Static

Scheduler Table

Calculates the HEC Byte for the Header of

an Outgoing Cell

Backward Compatible With the TNETA1570

in 32-Bit PCI Mode

Checks the HEC Byte of an Incoming Cell

UTOPIA Level 1-Compliant Cell Interface

Internal 32-Cell Receive FIFO

Provides Support for Available-Bit-Rate

(ABR) Traffic via External Coprocessor

Interface (COPI)

Cell Interface Can Be Programmed to

Operate as Either a Physical (PHY-Layer)

Interface or as a SAR/Switch (ATM-Layer)

Interface

Provides Support for VBR-nrt Traffic via

External COPI

Transmit-Channel Sleep Mode Prevents the

SAR Polling Channels When No Packets

Are Queued

Provides Reassembly Time Out for

Incoming Packets

Provides an Internal Loopback Capability

From Transmit to Receive

High-Performance Features Include Use of

Sideband Signals to Reduce Polling Across

the PCI Bus

Supports Boundary Scan Through a

Five-Wire JTAG Interface in Accordance

With IEEE Std 1149.1-1990 (Includes IEEE

Std 1149.1a-1993)

description

The TNETA1575 is an asynchronous transfer mode (ATM) segmentation and reassembly (SAR) device with

a peripheral component interconnect (PCI)-bus interface and a coprocessor interface (COPI). The TNETA1575

continues the line of Texas Instruments (TI) ATM SAR devices directed toward the classical LAN-to-ATM

translation market segment. Features have been extended to include the COPI interface, which interfaces to

an external scheduler with high-performance features to eliminate polling on the PCI bus. The TNETA1575 is

designed for the emerging class of high-performance enterprise networking hubs that utilize ATM in the

backplane, in addition to the traditional frame-/packet-based bus systems. Some of the features required for

this application include: high level of virtual channel/virtual path support, support for isochronous services, early

segmentation, and high-performance, 32-bit PCI-bus support. The feature set required by cell-operating

enterprisehubsisdifferentfromthesetsbeingofferedbyotherSARdevices, whicharedirectedprimarilytoward

the adapter card market.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Thundercell and TI are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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与TNETA1575PGC相关器件

型号	品牌	获取价格	描述	数据表
TNETA1585	TI	获取价格	ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
TNETA1585PCM	TI	获取价格	ATM traffic management scheduler 160-QFP 0 to 0
TNETA1585PGF	TI	获取价格	ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
TNETA1600	ETC	获取价格	Telecommunication IC
TNETA1600PCM	TI	获取价格	IC,ATM/SONET FRAMER,QFP,160PIN,PLASTIC
TNETA1611PCA	ETC	获取价格	ATM/SONET Transceiver
TNETA1622	TI	获取价格	622.08-MHz CLOCK-RECOVERY DEVICE
TNETA1622DW	ETC	获取价格	Clock/Data Recovery
TNETA1622DWR	TI	获取价格	暂无描述
TNETA1630DW	TI	获取价格	SPECIALTY TELECOM CIRCUIT, PDIP20

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