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TM4FJ64KPU-50 PDF预览

TM4FJ64KPU-50

更新时间： 2024-09-13 19:38:07
品牌 Logo 应用领域
德州仪器 - TI 动态存储器内存集成电路
页数 文件大小 规格书
24页 338K
描述
4MX64 EDO DRAM MODULE, 50ns, DMA144, SODIMM-144

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TM4FJ64KPU-50 技术参数

生命周期：Obsolete零件包装代码：MODULE
包装说明：SODIMM-144针数：144
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.24风险等级：5.84
访问模式：FAST PAGE WITH EDO最长访问时间：50 ns
其他特性：RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHI/O 类型：COMMON
JESD-30 代码：R-XDMA-N144内存密度：268435456 bit
内存集成电路类型：EDO DRAM MODULE内存宽度：64
功能数量：1端口数量：1
端子数量：144字数：4194304 words
字数代码：4000000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：4MX64输出特性：3-STATE
封装主体材料：UNSPECIFIED封装代码：DIMM
封装等效代码：DIMM144,32封装形状：RECTANGULAR
封装形式：MICROELECTRONIC ASSEMBLY电源：3.3 V
认证状态：Not Qualified刷新周期：4096
自我刷新：YES最大待机电流：0.0006 A
子类别：DRAMs最大压摆率：0.52 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子形式：NO LEAD端子节距：0.8 mm
端子位置：DUALBase Number Matches：1

TM4FJ64KPU-50 数据手册

 浏览型号TM4FJ64KPU-50的Datasheet PDF文件第2页浏览型号TM4FJ64KPU-50的Datasheet PDF文件第3页浏览型号TM4FJ64KPU-50的Datasheet PDF文件第4页浏览型号TM4FJ64KPU-50的Datasheet PDF文件第5页浏览型号TM4FJ64KPU-50的Datasheet PDF文件第6页浏览型号TM4FJ64KPU-50的Datasheet PDF文件第7页 
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT  
TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT  
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM  
SMMS693A – AUGUST 1997 – REVISED NOVEMBER 1997  
Organization  
Long Refresh Periods:  
– TM4xJ64xPU-xx . . . 4194304 × 64 Bits  
– TM8xJ64xPU-xx . . . 8388608 × 64 Bits  
– TMxEJ64KPU: 64 ms (4096 Cycles)  
– TMxEJ64NPU: 64 ms (8192 Cycles)  
– TMxFJ64KPU: 128 ms (4096 Cycles)  
– TMxFJ64NPU: 128 ms (8192 Cycles)  
Single 3.3-V Power Supply  
(±10% Tolerance)  
Extended Data Out (EDO) Operation With  
CAS-Before-RAS (CBR), RAS-Only, and  
Hidden Refresh  
JEDEC 144-Pin Small-Outline Dual-In-Line  
Memory Module (SODIMM) Without Buffer  
for Use With Socket  
Serial Presence-Detect (SPD) Using  
EEPROM  
TM4xJ64xPU-xx — Utilizes Four 64M-Bit  
High-Speed (4M×16-Bit) Dynamic RAMs  
Ambient Temperature Range  
0°C to 70°C  
TM4xJ64xPU-xx — Utilizes Eight 64M-Bit  
High-Speed (4M×16-Bit) Dynamic RAMs  
Performance Ranges  
High-Speed, Low-Noise LVTTL Interface  
ACCESS ACCESS ACCESS EDO  
High-Reliability 50-Lead 400-Mil-Wide  
Surface-Mount Thin Small-Outline Package  
(TSOP) (DGE Suffix)  
TIME  
TIME  
TIME CYCLE  
t
t
t
t
HPC  
RAC  
CAC  
AA  
(MAX)  
40 ns  
50 ns  
60 ns  
(MAX)  
11 ns  
13 ns  
15 ns  
(MAX)  
20 ns  
25 ns  
30 ns  
(MIN)  
16 ns  
20 ns  
25 ns  
3-State Output  
’xxJ64xPU-40  
’xxJ64xPU-50  
’xxJ64xPU-60  
Gold-Plated Contacts  
description  
The TM4xJ64KPU is a 32M-byte, 144-pin, small-outline dual-in-line memory module (SODIMM). The SODIMM  
is composed of four TMS465169/P, 4194304 × 16-bit 4K normal or low-power battery-backup refresh EDO  
dynamic random-access memory (DRAM) devices, each in a 400-mil, 50-pin plastic thin small-outline package  
(TSOP) (DGE suffix) package mounted on a substrate with decoupling capacitors. See the TMS465169/P data  
sheet (literature number SMHS566).  
The TM4xJ64NPU is a 32M-byte, 144-pin SODIMM. The SODIMM is composed of four TMS464169/P,  
4194304× 16-bit8Knormalorlow-powerbattery-backuprefreshEDODRAMs, eachina400-mil, 50-pinplastic  
TSOP (DGE suffix) mounted on a substrate with decoupling capacitors. See the TMS464169/P data sheet  
(literature number SMHS566).  
The TM8xJ64KPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS465169/P,  
4194304× 16-bit4Knormalorlow-powerbattery-backuprefreshEDODRAMs, eachina400-mil, 50-pinplastic  
TSOP (DGE suffix) mounted on a substrate with decoupling capacitors.  
The TM8xJ64NPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS464169/P,  
4194304× 16-bit8Knormalorlow-powerbattery-backuprefreshEDODRAMs, eachina400-mil, 50-pinplastic  
TSOP (DGE suffix) mounted on a substrate with decoupling capacitors.  
operation  
The TM4xJ64xPU operates as four TMS46x169/Ps that are connected as shown in the TMxxJ64xPU functional  
block diagram. The TM8xJ64xPU operates as eight TMS46x169/Ps that are connected as shown in the  
TMxxJ64xPU functional block diagram.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...24

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