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TM4SR72EPH-10 PDF预览

TM4SR72EPH-10

更新时间： 2024-01-06 15:12:27
品牌 Logo 应用领域
德州仪器 - TI 时钟动态存储器光电二极管
页数 文件大小 规格书
15页 235K
描述
MEMORY MODULE,SDRAM,4MX72,CMOS,DIMM,168PIN,PLASTIC

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TM4SR72EPH-10 技术参数

生命周期：Obsolete零件包装代码：DIMM
包装说明：DIMM-168针数：168
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.28风险等级：5.84
Is Samacsys：N访问模式：DUAL BANK PAGE BURST
最长访问时间：7 nsJESD-30 代码：R-XDMA-N168
内存密度：301989888 bit内存集成电路类型：SYNCHRONOUS DRAM MODULE
内存宽度：72功能数量：1
端口数量：1端子数量：168
字数：4194304 words字数代码：4000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4MX72
封装主体材料：UNSPECIFIED封装形状：RECTANGULAR
封装形式：MICROELECTRONIC ASSEMBLY认证状态：Not Qualified
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子形式：NO LEAD端子位置：DUAL
Base Number Matches：1

TM4SR72EPH-10 数据手册

 浏览型号TM4SR72EPH-10的Datasheet PDF文件第2页浏览型号TM4SR72EPH-10的Datasheet PDF文件第3页浏览型号TM4SR72EPH-10的Datasheet PDF文件第4页浏览型号TM4SR72EPH-10的Datasheet PDF文件第5页浏览型号TM4SR72EPH-10的Datasheet PDF文件第6页浏览型号TM4SR72EPH-10的Datasheet PDF文件第7页 
TM2SR72EPH 2097152 BY 72-BIT  
TM4SR72EPH 4194304 BY 72-BIT  
SYNCHRONOUS DYNAMIC RAM MODULES  
SMMS705A – FEBRUARY 1998 – REVISED APRIL 1998  
Organization  
– TM2SR72EPH . . . 2097152 x 72 Bits  
– TM4SR72EPH . . . 4194304 x 72 Bits  
High-Speed, Low-Noise Low-Voltage TTL  
(LVTTL) Interface  
Byte-Read/Write Capability  
Single 3.3-V Power Supply  
(±10% Tolerance)  
Read Latencies 2 and 3 Supported  
Support Burst-Interleave and  
Burst-Interrupt Operations  
Designed for 66-MHz 4-Clock Systems  
JEDEC 168-Pin Dual-In-Line Memory  
Module (DIMM) Without Buffer for Use With  
Socket  
Burst Length Programmable to 1, 2, 4,  
and 8  
Two Banks for On-Chip Interleaving  
(Gapless Access)  
TM2SR72EPH — Uses Nine 16M-Bit  
Synchronous Dynamic RAMs (SDRAMs)  
(2M × 8-Bit) in Plastic Thin Small-Outline  
Packages (TSOPs)  
Ambient Temperature Range  
0°C to 70°C  
Gold-Plated Contacts  
Pipeline Architecture  
TM4SR72EPH — Uses 18 16M-Bit SDRAMs  
(2M × 8-Bit) in Plastic TSOPs  
Serial Presence Detect (SPD) Using  
EEPROM  
Performance Ranges:  
SYNCHRONOUS  
CLOCK CYCLE  
TIME  
ACCESS TIME  
(CLOCK TO  
OUTPUT)  
REFRESH  
INTERVAL  
t
t
t
t
AC2  
CK3  
CK2  
AC3  
†
(CL = 3)  
(CL = 2) (CL = 3) (CL = 2)  
’xSR72EPH-10  
10 ns  
15 ns 7.5 ns 7.5 ns  
64 ms  
†
CL = CAS latency  
description  
The TM2SR72EPH is a 16M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of nine  
TMS626812BDGE, 2097152 × 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package  
(TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812B data sheet (literature  
number SMOS693).  
The TM4SR72EPH is a 32M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS626812BDGE,  
2097152 × 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling  
capacitors. See the TMS626812B data sheet (literature number SMOS693).  
operation  
The TM2SR72EPH operates as nine TMS626812BDGE devices that are connected as shown in the  
TM2SR72EPH functional block diagram. The TM4SR72EPH operates as eighteen TMS626812BDGE devices  
connected as shown in the TM4SR72EPH functional block diagram.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...15

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