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TM4SN64EPU PDF预览

TM4SN64EPU

更新时间: 2024-11-04 21:53:19
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
16页 273K
描述
SYNCHRONOUS DYNAMIC RAM MODULES

TM4SN64EPU 数据手册

 浏览型号TM4SN64EPU的Datasheet PDF文件第2页浏览型号TM4SN64EPU的Datasheet PDF文件第3页浏览型号TM4SN64EPU的Datasheet PDF文件第4页浏览型号TM4SN64EPU的Datasheet PDF文件第5页浏览型号TM4SN64EPU的Datasheet PDF文件第6页浏览型号TM4SN64EPU的Datasheet PDF文件第7页 
TM2SN64EPU 2097152 BY 64-BIT  
TM4SN64EPU 4194304 BY 64-BIT  
SYNCHRONOUS DYNAMIC RAM MODULES  
SMMS681 – AUGUST 1997  
Organization:  
– TM2SN64EPU . . . 2 097 152 x 64 Bits  
– TM4SN64EPU . . . 4 194 304 x 64 Bits  
High-Speed, Low-Noise Low-Voltage TTL  
(LVTTL) Interface  
Read Latencies 2 and 3 Supported  
Single 3.3-V Power Supply  
(±10% Tolerance)  
Support Burst-Interleave and  
Burst-Interrupt Operations  
Designed for 66-MHz 4-Clock Systems  
Burst Length Programmable to 1, 2, 4,  
and 8  
JEDEC 168-Pin Dual-In-Line Memory  
Module (DIMM) Without Buffer for Use With  
Socket  
Two Banks for On-Chip Interleaving  
(Gapless Access)  
TM2SN64EPU — Uses Eight 16M-Bit  
Synchronous Dynamic RAMs (SDRAMs)  
(2M × 8-Bit) in Plastic Thin Small-Outline  
Packages (TSOPs)  
Ambient Temperature Range  
0°C to 70°C  
Gold-Plated Contacts  
Pipeline Architecture  
TM4SN64EPU — Uses Sixteen 16M-Bit  
SDRAMs (2M × 8-Bit) in Plastic TSOPs  
Serial Presence-Detect (SPD) Using  
EEPROM  
Byte-Read/Write Capability  
Performance Ranges:  
SYNCHRONOUS  
CLOCK CYCLE  
TIME  
ACCESS TIME  
CLOCK TO  
OUTPUT  
REFRESH  
INTERVAL  
t
t
t
t
CK2  
CK3  
CK2  
CK3  
(CL = 3)  
(CL = 2) (CL = 3) (CL = 2)  
’xSN64EPU-12A  
12 ns  
15 ns  
18 ns  
9 ns  
9 ns  
9 ns  
64 ms  
64 ms  
’xSN64EPU-12  
12 ns  
10 ns  
CL = CAS latency  
–12A speed device is supported only at –5 to +10% V  
DD  
description  
The TM2SN64EPU is a 16M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of  
eight TMS626812DGE, 2097152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package  
(TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812 data sheet (literature number  
SMOS687).  
The TM4SN64EPU is a 32M-byte, 168-pin DIMM. The DIMM is composed of sixteen TMS626812DGE,  
2097152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling  
capacitors. See the TMS626812 data sheet (literature number SMOS687).  
operation  
The TM2SN64EPU operates as eight TMS626812DGE devices that are connected as shown in the  
TM2SN64EPU functional block diagram. The TM4SN64EPU operates as 16 TMS626812DGE devices  
connected as shown in the TM4SN64EPU functional block diagram.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443  

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