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SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
D
Organization
− TM4xJ64xPU-xx . . . 4194304 × 64 Bits
− TM8xJ64xPU-xx . . . 8388608 × 64 Bits
Single 3.3-V Power Supply
( 10% Tolerance)
D
Long Refresh Periods:
− TMxEJ64KPU: 64 ms (4096 Cycles)
− TMxEJ64NPU: 64 ms (8192 Cycles)
− TMxFJ64KPU: 128 ms (4096 Cycles)
− TMxFJ64NPU: 128 ms (8192 Cycles)
D
D
D
Extended Data Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
JEDEC 144-Pin Small-Outline Dual-In-Line
Memory Module (SODIMM) Without Buffer
for Use With Socket
D
D
D
Serial Presence-Detect (SPD) Using
EEPROM
D
D
TM4xJ64xPU-xx — Utilizes Four 64M-Bit
High-Speed (4M×16-Bit) Dynamic RAMs
TM4xJ64xPU-xx — Utilizes Eight 64M-Bit
High-Speed (4M×16-Bit) Dynamic RAMs
Ambient Temperature Range
0°C to 70°C
Performance Ranges
D
High-Speed, Low-Noise LVTTL Interface
ACCESS ACCESS ACCESS EDO
D
High-Reliability 50-Lead 400-Mil-Wide
Surface-Mount Thin Small-Outline Package
(TSOP) (DGE Suffix)
TIME
TIME
TIME CYCLE
t
t
t
t
HPC
RAC
CAC
AA
(MAX)
40 ns
50 ns
60 ns
(MAX)
11 ns
13 ns
15 ns
(MAX)
20 ns
25 ns
30 ns
(MIN)
16 ns
20 ns
25 ns
D
D
3-State Output
’xxJ64xPU-40
’xxJ64xPU-50
’xxJ64xPU-60
Gold-Plated Contacts
description
The TM4xJ64KPU is a 32M-byte, 144-pin, small-outline dual-in-line memory module (SODIMM). The SODIMM
is composed of four TMS465169/P, 4194304 × 16-bit 4K normal or low-power battery-backup refresh EDO
dynamic random-access memory (DRAM) devices, each in a 400-mil, 50-pin plastic thin small-outline package
(TSOP) (DGE suffix) package mounted on a substrate with decoupling capacitors. See the TMS465169/P data
sheet (literature number SMHS566).
The TM4xJ64NPU is a 32M-byte, 144-pin SODIMM. The SODIMM is composed of four TMS464169/P,
4194304 × 16-bit 8K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic
TSOP (DGE suffix) mounted on a substrate with decoupling capacitors. See the TMS464169/P data sheet
(literature number SMHS566).
The TM8xJ64KPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS465169/P,
4194304 × 16-bit 4K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic
TSOP (DGE suffix) mounted on a substrate with decoupling capacitors.
The TM8xJ64NPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS464169/P,
4194304 × 16-bit 8K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic
TSOP (DGE suffix) mounted on a substrate with decoupling capacitors.
operation
The TM4xJ64xPU operates as four TMS46x169/Ps that are connected as shown in the TMxxJ64xPU functional
block diagram. The TM8xJ64xPU operates as eight TMS46x169/Ps that are connected as shown in the
TMxxJ64xPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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ꢩ ꢯꢧ ꢢ ꢱꢪ ꢤꢥ ꢭꢡ ꢫ ꢩ ꢤꢢ ꢨꢡ ꢢꢮꢪ ꢨ ꢯꢪ ꢫ ꢪ ꢬꢥ ꢤꢭ ꢮꢩꢨ ꢫ ꢵ ꢡꢨꢯ ꢤꢮꢨ ꢢꢤꢨ ꢡꢩꢪ ꢳ
Copyright 1997, Texas Instruments Incorporated
1
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