Datasheet > TC55VDM536AFFN15

TC55VDM536AFFN15

更新时间： 2024-09-19 20:37:39

品牌	Logo	应用领域
东芝 - TOSHIBA		静态存储器内存集成电路
页数	文件大小	规格书
22页	503K
描述
IC 1M X 36 ZBT SRAM, 3.8 ns, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100, Static RAM

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TC55VDM536AFFN15 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	3.8 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	37748736 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	36
功能数量：	1	端子数量：	100
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1MX36
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	1.7 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

TC55VDM536AFFN15 数据手册

TC55VDM536AFFN22/20/16/15

TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

36M 3.3V Pipelined NtRAM^TM1M Word by 36Bit

SYNCHRONOUS NO-TURNAROUND STATIC RAM

DESCRIPTION

The TC55VDM536AFFN is a synchronous static random access memory (SRAM) organized as 1,048,576 words

by 36 bits. NtRAM^TM(no-turnaround SRAM) offers high bandwidth by eliminating dead cycles during the

transition from a read to a write and vice versa. All inputs except Output Enable OE and the Snooze pin ZZ are

synchronized with the rising edge of the CLK input. A Read operation is initiated by the ADV Address Advanced

Input signal ; the input from the address pins and all control pins except the OE and ZZ pins are loaded into the

internal registers on the rising edge of CLK in the cycle in which ADV is asserted. The output data is available two

clock cycles later. Write operations are internally self-timed and are initiated by the rising edge of CLK in the cycle

in which ADV is asserted. The input from the address pins and all control pins except the OE and ZZ pins are

loaded into the internal registers on the rising edge of CLK in the cycle in which ADV is asserted. Input data is

loaded in the third cycle after the cycle in which ADV is asserted. Byte Write Enables ( BW1 to BW4 ) allow from

one to four Byte Write operations to be performed. A 2-bit burst address counter and control logic are integrated

into this SRAM. The TC55VDM536AFFN uses a single power supply (3.3 V) or dual power supplies (3.3 V for core

and 2.5 V for output buffer) and is available in a 100-pin low-profile plastic QFP (LQFP).

FEATURES

•

Organized as 1,048,576 words by 36 bits

No-turnaround operation with pipeline data output

2-bit burst address counter

•

Single 3.3V 5% power supply V_DD

Dual 3.3 V or 2.5 V power supply V_DDQ

Available in 100-pin LQFP package

(support for interleaved or linear burst sequences)

Synchronous self-timed Write

(LQFP100-P-1420-0.65B ; weight :

grams

•

(typical))

Byte Write control

MHz

225

4.4

2.8

200

167

6.0

3.5

150

6.6

3.8

Snooze mode pin (ZZ) for power down

LVTTL-compatible interface

Clock Cycle Time

Clock Access Time

Operating Current I_DDO1

t_KC

t_KQV

5.0

3.2

TBD

PIN ASSIGNMENT (TOP VIEW)

PIN NAMES

CLK

Clock Input

Address Inputs

A0 to A19

99 97 95 93 91 89 87 85 83 81

100 98 96 94 92 90 88 86 84 82

I/OP3

I/O17

I/O18

V^DDQ

V^SSQ

I/O19

I/O20

I/O21

I/O22

V^SSQ

V^DDQ

I/O23

I/O24

V^DD

I/OP2

I/O16

I/O15

V^DDQ

V^SSQ

I/O14

I/O13

I/O12

I/O11

V^SSQ

V^DDQ

I/O10

I/O9

CE , CE2 , CE2 Chip Enable Inputs

Output Enable Input

Write Enable input

BW1 to BW4 Byte Write Enable

ADV

CKE

Address Advance Input

Clock Enable

V^SS

Snooze Input

V^DD

V^SS

V^DD

I/O1 to I/O32

Data Inputs/Outputs

I/O25

I/O26

V^DDQ

V^SSQ

I/O27

I/O28

I/O29

I/O30

V^SSQ

V^DDQ

I/O31

I/O32

I/OP4

I/O8

I/OP1 to I/OP4 Parity Data Inputs/Outputs

I/O7

V^DDQ

V^SSQ

I/O6

MODE

Mode select Input

No Connection

I/O5

I/O4

Not Usable

I/O3

V^SSQ

V^DDQ

I/O2

Power Supply for Core

Power Supply for Output Buffer

Ground for Core

I/O1

DDQ

32 34 36 38 40 42 44 46 48 50

31 33 35 37 39 41 43 45 47 49

I/OP1

Ground for Output Buffer

SSQ

Note :

NtRAM

and No-Turnaround Random Access

Memory are trademarks of Samsung Electronics Co., Ltd..

2003-01-08 1/22

12 3 4 5 6 7...22

中文翻译

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与TC55VDM536AFFN15相关器件

型号	品牌	获取价格	描述	数据表
TC55VDM536AFFN20	TOSHIBA	获取价格	IC 1M X 36 ZBT SRAM, 3.2 ns, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100, Static
TC55VEM208ASGN55	TOSHIBA	获取价格	IC 512K X 8 STANDARD SRAM, 70 ns, PDSO32, 0.50 MM PITCH, PLASTIC, LEAD FREE, TSOP1-32, Sta
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TC55VEM208ASTN55	TOSHIBA	获取价格	TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
TC55VEM216ABXN55	TOSHIBA	获取价格	IC 256K X 16 STANDARD SRAM, 70 ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, PLASTIC, TFBGA-48, Sta
TC55VEM216AGXN40	TOSHIBA	获取价格	IC 256K X 16 STANDARD SRAM, 55 ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, LEAD FREE, PLASTIC, TF
TC55VEM216AGXN55	TOSHIBA	获取价格	IC 256K X 16 STANDARD SRAM, 70 ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, LEAD FREE, PLASTIC, TF
TC55VEM216AXBN40	TOSHIBA	获取价格	IC 256K X 16 STANDARD SRAM, 40 ns, PBGA48, 6 X 7 MM, 0.75 MM PITCH, PLASTIC, TFBGA-48, Sta
TC55VEM216AXBN55	TOSHIBA	获取价格	IC 256K X 16 STANDARD SRAM, 55 ns, PBGA48, 6 X 7 MM, 0.75 MM PITCH, PLASTIC, TFBGA-48, Sta
TC55VEM316AXBN	TOSHIBA	获取价格	TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

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