Datasheet > SY100S302_07

SY100S302_07

更新时间： 2024-11-27 07:20:11

品牌	Logo	应用领域
麦瑞 - MICREL		输入元件
页数	文件大小	规格书
4页	79K
描述
QUINT 2-INPUT OR/NOR GATE

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SY100S302_07 数据手册

SY100S302

Micrel, Inc.

QUINT 2-INPUT

OR/NOR GATE

FEATURES

DESCRIPTION

■ Max. propagation delay of 700ps

■ IEE min. of –45mA

The SY100S302 offers five 2-input OR/NOR gates

designed for use in high-performance ECL systems. The

five gates are controlled by a common Enable signal. All

inputs have 75kΩ pull-down resistors and all outputs are

buffered.

■ Industry standard 100K ECL levels

■ Extended supply voltage option:

VEE = –4.2V to –5.5V

■ Voltage and temperature compensation for

improved noise immunity

■ Internal 75kΩ input pull-down resistors

■ 50% faster than Fairchild 300K

■ Function and pinout compatible with Fairchild F100K

■ Available in 28-pin PLCC package

BLOCK DIAGRAM

PIN NAMES

Dna – Dne

Function

Data Inputs (n-1...5)

Enable Input

Oa – Oe

VEES

Data Outputs

Complementary Data Outputs

VEE Substrate

VCCA

VCCO for ECL Outputs

Rev.: I

Amendment:/0

M9999-042307

hbwhelp@micrel.com or (408) 955-1690

Issue Date: April 2007

12 3 4

中文翻译

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