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SY100S302FC

更新时间： 2024-11-23 22:35:59

品牌	Logo	应用领域
麦瑞 - MICREL		输入元件
页数	文件大小	规格书
5页	100K
描述
QUINT 2-INPUT OR/NOR GATE

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中文翻译

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数据手册

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SY100S302FC 数据手册

QUINT 2-INPUT

OR/NOR GATE

SY100S302

FEATURES

DESCRIPTION

■ Max. propagation delay of 700ps

■ IEE min. of –45mA

The SY100S302 offers five 2-input OR/NOR gates

designed for use in high-performance ECL systems. The

five gates are controlled by a common Enable signal. All

inputs have 75KΩ pull-down resistors and all outputs are

buffered.

■ Industry standard 100K ECL levels

■ Extended supply voltage option:

VEE = –4.2V to –5.5V

■ Voltage and temperature compensation for

PIN CONFIGURATIONS

improved noise immunity

■ Internal 75KΩ input pull-down resistors

■ 50% faster than Fairchild 300K

■ Function and pinout compatible with Fairchild F100K

11 10 9

8 7 6 5

D1b

D2b

VEE

VEES

■ Available in 24-pin CERPACK and 28-pin PLCC

packages

Top View

PLCC

J28-1

VCCA

VCC

D1c

D2c

19 20 21 22 23 24 25

BLOCK DIAGRAM

24 23 22 21 20 19

Top View

Flatpack

F24-1

8 9 10 11 12

PIN NAMES

Dna – Dne

Function

Data Inputs (n-1...5)

Enable Input

Oa – Oe

VEES

Data Outputs

Complementary Data Outputs

VEE Substrate

VCCA

VCCO for ECL Outputs

Rev.: G

Amendment:/0

Issue Date: July, 1999

12 3 4 5

中文翻译

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