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SY100S307JCTR

更新时间： 2024-11-10 22:06:47

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
5页	100K
描述
QUINT EXCLUSIVE OR/NOR GATE

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中文翻译

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数据手册

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SY100S307JCTR 数据手册

QUINT EXCLUSIVE

OR/NOR GATE

SY100S307

FEATURES

DESCRIPTION

The SY100S307 is an ultra-fast quint exclusive-OR/

NOR gate designed for use in high-performance ECL

systems. A function output that is the wire-OR result of the

exclusive-OR outputs is also available. The inputs on the

device have 75KΩ pull-down resistors.

■ Max. propagation delay of 1000ps

■ IEE min. of –58mA

■ Extended supply voltage option:

VEE = –4.2V to –5.5V

■ Voltage and temperature compensation for improved

noise immunity

PIN CONFIGURATIONS

■ Internal 75KΩ input pull-down resistors

■ 50% faster than Fairchild 300K at lower power

■ Function and pinout compatible with Fairchild F100K

11 10 9

8 7 6 5

■ Available in 24-pin CERPACK and 28-pin PLCC

packages

EES

CCA

Top View

PLCC

J28-1

BLOCK DIAGRAM

19 20 21 22 23 24 25

24 23 22 21 20 19

Top View

Flatpack

F24-1

8 9 10 11 12

PIN NAMES

Dna – Dne

Function

Data Inputs (n-1...5)

Enable Input

Oa – Oe

VEES

Data Outputs

Complementary Data Outputs

VEE Substrate

VCCA

VCCO for ECL Outputs

Rev.: G

Amendment:/0

Issue Date: July, 1999

12 3 4 5

中文翻译

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SY100S307JY	MICREL	获取价格	QUINT EXCLUSIVE OR/NOR GATE
SY100S307JY	MICROCHIP	获取价格	100S SERIES, 5 2-INPUT XOR/XNOR GATE, PQCC28
SY100S307JYTR	MICREL	获取价格	QUINT EXCLUSIVE OR/NOR GATE
SY100S307JZ	MICREL	获取价格	QUINT EXCLUSIVE OR/NOR GATE
SY100S307JZ	MICROCHIP	获取价格	100S SERIES, 5 2-INPUT XOR/XNOR GATE, PQCC28
SY100S307JZTR	MICREL	获取价格	QUINT EXCLUSIVE OR/NOR GATE
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