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SY100S307FC-TR PDF预览

SY100S307FC-TR

更新时间: 2024-11-11 20:10:55
品牌 Logo 应用领域
美国微芯 - MICROCHIP 逻辑集成电路石英晶振触发器
页数 文件大小 规格书
6页 84K
描述
XOR/XNOR GATE

SY100S307FC-TR 技术参数

生命周期:Active包装说明:QFF, QFL24,.4SQ
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.61JESD-30 代码:S-GQFP-F24
长度:9.78 mm逻辑集成电路类型:XOR/XNOR GATE
功能数量:5输入次数:2
端子数量:24最高工作温度:85 °C
最低工作温度:封装主体材料:CERAMIC, GLASS-SEALED
封装代码:QFF封装等效代码:QFL24,.4SQ
封装形状:SQUARE封装形式:FLATPACK
包装方法:TR最大电源电流(ICC):58 mA
Prop。Delay @ Nom-Sup:1.15 ns传播延迟(tpd):1.15 ns
施密特触发器:NO座面最大高度:2.29 mm
表面贴装:YES技术:ECL
温度等级:OTHER端子形式:FLAT
端子节距:1.27 mm端子位置:QUAD
宽度:9.78 mmBase Number Matches:1

SY100S307FC-TR 数据手册

 浏览型号SY100S307FC-TR的Datasheet PDF文件第2页浏览型号SY100S307FC-TR的Datasheet PDF文件第3页浏览型号SY100S307FC-TR的Datasheet PDF文件第4页浏览型号SY100S307FC-TR的Datasheet PDF文件第5页浏览型号SY100S307FC-TR的Datasheet PDF文件第6页 
SY100S307  
QUINT EXCLUSIVE  
OR/NOR GATE  
FEATURES  
DESCRIPTION  
The SY100S307 is an ultra-fast quint exclusive-OR/  
NOR gate designed for use in high-performance ECL  
systems. A function output that is the wire-OR result of the  
exclusive-OR outputs is also available. The inputs on the  
device have 75Kpull-down resistors.  
Max. propagation delay of 1000ps  
IEE min. of –58mA  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Voltage and temperature compensation for improved  
noise immunity  
Internal 75Kinput pull-down resistors  
50% faster than Fairchild 300K at lower power  
Function and pinout compatible with Fairchild F100K  
Available in 24-pin CERPACK and 28-pin PLCC  
packages  
BLOCK DIAGRAM  
PIN NAMES  
Pin  
Dna – Dne  
E
Function  
Data Inputs (n-1...5)  
F
D
D
1a  
2a  
O
O
a
a
Enable Input  
Oa – Oe  
Oa – Oe  
VEES  
Data Outputs  
Complementary Data Outputs  
VEE Substrate  
D
D
1b  
2b  
O
O
b
b
VCCA  
VCCO for ECL Outputs  
D
D
1c  
2c  
O
O
c
c
D
D
1d  
2d  
O
O
d
d
D
D
1e  
2e  
O
O
e
e
Rev.: H  
Amendment:/0  
M9999-032206  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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