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SY100S304JZ-TR PDF预览

SY100S304JZ-TR

更新时间: 2024-11-24 13:02:43
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麦瑞 - MICREL /
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SY100S304JZ-TR 数据手册

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SY100S304  
QUINT  
AND/NAND GATE  
FEATURES  
DESCRIPTION  
The SY100S304 is an ultra-fast quint AND/NAND gate  
designed for use in high-performance ECL systems. This  
device also features a Function (F) output which is the wire-  
NOR of the AND gate outputs. The inputs on the device  
have 75kpull-down resistors.  
Max. propagation delay of 1050ps  
IEE min. of –60mA  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Voltage and temperature compensation for improved  
noise immunity  
Internal 75kinput pull-down resistors  
40% faster than Fairchild 300K at lower power  
Function and pinout compatible with Fairchild F100K  
Available in 28-pin PLCC package  
PIN NAMES  
BLOCK DIAGRAM  
Pin  
Dna – Dne  
E
Function  
Data Inputs (n-1...5)  
F
Enable Input  
D
D
1a  
2a  
O
O
a
a
Oa – Oe  
Oa – Oe  
VEES  
Data Outputs  
Complementary Data Outputs  
VEE Substrate  
D
D
1b  
2b  
O
O
b
b
VCCA  
VCCO for ECL Outputs  
D
D
1c  
2c  
O
O
c
c
D
D
1d  
2d  
O
O
d
d
D
D
1e  
2e  
O
O
e
e
Rev.: I  
Amendment:/0  
M9999-042307  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: April 2007  

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