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SY100S307FCTR PDF预览

SY100S307FCTR

更新时间: 2024-11-24 13:14:11
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
4页 359K
描述
IC,LOGIC GATE,2/2/2/2/2 XOR-OR,ECL100,QFL,24PIN,CERAMIC

SY100S307FCTR 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:QFF, QFL24,.4SQReach Compliance Code:compliant
风险等级:5.86JESD-30 代码:S-XQFP-F24
JESD-609代码:e0端子数量:24
最高工作温度:85 °C最低工作温度:
封装主体材料:CERAMIC封装代码:QFF
封装等效代码:QFL24,.4SQ封装形状:SQUARE
封装形式:FLATPACK包装方法:TAPE AND REEL
电源:-4.5 V最大电源电流(ICC):58 mA
Prop。Delay @ Nom-Sup:1.1 ns认证状态:Not Qualified
施密特触发器:NO子类别:Gates
表面贴装:YES技术:ECL100K
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:QUADBase Number Matches:1

SY100S307FCTR 数据手册

 浏览型号SY100S307FCTR的Datasheet PDF文件第2页浏览型号SY100S307FCTR的Datasheet PDF文件第3页浏览型号SY100S307FCTR的Datasheet PDF文件第4页 
7  
SY100S307  
QUINTꢀEXCLUSIVE  
OR/NORꢀGATE  
FEATURES  
DESCRIPTION  
The SY100S307 is an ultra-fast quint exclusive-OR/NOR  
gate designed for use in high-performance ECL systems. A  
function output that is the wire-OR result of the exclusive-OR  
outputs is also available. The inputs on the device have 75kΩ  
pull-down resistors.  
■ꢀ Max.ꢀpropagationꢀdelayꢀofꢀ1000ps  
■ꢀ IEEꢀmin.ꢀofꢀ–58mA  
■ꢀ Extendedꢀsupplyꢀvoltageꢀoption:  
VEEꢀ=ꢀ–4.2Vꢀtoꢀ–5.5V  
■ꢀ Voltageꢀandꢀtemperatureꢀcompensationꢀforꢀimprovedꢀ  
noiseꢀimmunity  
■ꢀ Internalꢀ75kΩꢀinputꢀpull-downꢀresistors  
■ꢀ 50%ꢀfasterꢀthanꢀFairchildꢀ300Kꢀatꢀlowerꢀpower  
■ꢀ FunctionꢀandꢀpinoutꢀcompatibleꢀwithꢀFairchildꢀF100K  
■ꢀ Availableꢀinꢀ28-pinꢀPLCCꢀpackage  
ꢁLOCKꢀDIAGRAM  
PINꢀNAMES  
Pinꢀ  
Dna – Dne  
E
Function  
Data Inputs (n-1...5)  
Enable Input  
Oa – Oe  
Oa – Oe  
VEES  
Data Outputs  
Complementary Data Outputs  
VEE Substrate  
VCCA  
VCCO for ECL Outputs  
Rev.: I  
Amendment: /0  
M9999-060910  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: June 2010  

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